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PDF ICS1562B Data sheet ( Hoja de datos )

Número de pieza ICS1562B
Descripción User-programmable differential Output Graphics Clock Generator
Fabricantes Integrated Circuit System 
Logotipo Integrated Circuit System Logotipo



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Integrated
Circuit
Systems, Inc.
ICS1562B
User Programmable Differential Output Graphics Clock Generator
Description
Features
The ICS1562B is a very high performance monolithic phase- Two programming options:
locked loop (PLL) frequency synthesizer. Utilizing ICS’s ad-
ICS1562B-001 (Parallel Programming)
vanced CMOS mixed-mode technology, the ICS1562B
ICS1562B-201 (Serial Programming)
provides a low cost solution for high-end video clock genera-
tion.
Supports high-resolution graphics - CLK output to
260 MHz, with 400 MHz options available
The ICS1562B has differential video clock outputs (CLK+ and Eliminates need for multiple ECL output crystal oscillators
CLK-) that are compatible with industry standard video DAC. Fully programmable synthesizer capability - not just a
Another clock output, LOAD, is provided whose frequency is
clock multiplier
derived from the main clock by a programmable divider. An Circuitry included for reset of Brooktree RAMDAC pipe-
additional clock output is available, LD/N2, which is derived
from the LOAD frequency and whose modulus may also be
line delay
programmed.
VRAM shift clock generation capability
(-201 option only)
Operating frequencies are fully programmable with direct con- Line-locked clock generation capability
trol provided for reference divider, prescaler, feedback divider External feedback loop capability (-201 option only)
and post-scaler.
Compact - 16-pin 0.150” skinny SOIC package
Reset of the pipeline delay on Brooktree RAMDACs may Fully backward compatible to ICS1562
be performed under register control. Outputs may also be set
to desired states to facilitate circuit board testing.
Simplified Block Diagram - ICS1562B
XTAL1
XTAL2
CRYSTAL
OSCILLATOR
/ R PHASE-
FREQUENCY
DETECTOR
EXTFBK
BLANK
(-201 only)
MUX
LOOP
FILTER
CHARGE
PUMP
VCO
PRESCALER
/M /A
ICS1562B - 001 Pinout
AD0
XTAL1
XTAL2
STROBE
VSS
VSS
LOAD
LD/N2
1
2
3
4
5
6
7
8
16 AD1
15 AD2
14 AD3
13 VDD
12 VDDO
11 IPRG
10 CLK+
9 CLK-
PROGRAMMING
INTERFACE
FEEDBACK DIVIDER
16-Pin SOIC
/2
/4
tasheet4u.comFigure 1
aRAMDAC is a trademark of Brooktree Corporation.
www.d1562 B Rev A 02/2/601
MUX
DIFF.
OUTPUT
/ N1
MUX
DRIVER
/ N2 DRIVER
CLK+
CLK
ICS1562B - 201 Pinout
LOAD
LD/N2
EXTFBK
XTAL1
XTAL2
DATCLK
VSS
VSS
LOAD
LD/N2
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
16-Pin SOIC
DATA
HOLD
BLANK
VDD
VDDO
IPRG
CLK+
CLK-

1 page




ICS1562B pdf
ICS1562B
External Feedback Operation
Power-On Initialization
The ICS1562B-201 option also supports the inclusion of an
external counter as the feedback divider of the PLL. This mode
is useful in graphic systems that must be “genlocked” to
external video sources.
When the EXTFBEN bit is set to logic 1, the phase-frequency
detector will use the EXTFBK pin as its feedback input. The
loop phase will be locked to the rising edges of the signal applied
to the EXTFBK input if the FBKPOL bit is set to logic 0.
VRAM Shift Clock Generation
The ICS1562B has an internal power-on reset circuit that
performs the following functions:
1) Sets the multiplexer to pass the reference frequency
to the CLK+ and CLK- outputs.
2) Selects the modulus of the N1 divider (for the
LOAD clock) to be four.
These functions should allow initialization of most graphics
systems that cannot immediately provide for register program-
ming upon system power-up.
The ICS1562B-201 option supports VRAM shift clock gen-
eration and interruption. By programming the N2 counter to
divide by 1, the LD/N2 output becomes a duplicate of the
LOAD output. When the SCEN bit is set, the LD/N2 output
may be synchronously started and stopped via the blank pin.
When BLANK is high, the LD/N2 will be free-running and in
phase with LOAD. When BLANK is taken low, the LD/N2
output is stopped at a low level. See Figure 5 for a diagram of
the sequence. Note that this use of the BLANK pin precludes its
use for phase comparator disable (see Line-Locked Operation).
VRAM Shift Clock Control
BLANK
LOAD
LD/N2
Because the power-on reset circuit is on the VDD supply, and
because that supply is filtered, care must be taken to allow the
reset to de-assert before programming. A safe guideline is to
allow 20 microseconds after the VDD supply reaches 4 volts.
Programming Notes
VCO Frequency Range: Use the post-divider to keep the
VCO frequency as high as possible within its operating
range.
Divider Range: For best results in normal situations (i.e,
pixel clock generation for hi-res displays), keep the refer-
ence divider modulus as short as possible (for a frequency
at the output of the reference divider in the few hundred
kHz to several MHz range). If you need to go to a lower
phase comparator reference frequency (usually required
for increased frequency accuracy), that is acceptable, but
jitter performance will suffer somewhat.
VCO Gain Programming: Use the minimum gain which
can reliably achieve the VCO frequency desired, as shown
on the following page:
Figure 5
5

5 Page





ICS1562B arduino
ICS1562B
Register Mapping - ICS1562B-201 (Serial Programming Option)
NOTE: IT IS NOT NECESSARY TO UNDERSTAND THE FUNCTION OF THESE BITS TO USE THE ICS1562B. PC SOFTWARE IS AVAILABLE
FROM ICS TO AUTOMATICALLY GENERATE ALL REGISTER VALUES BASED ON REQUIREMENTS. CONTACT FACTORY FOR DETAILS.
BIT(S)
BIT REF.
DESCRIPTION
1-4
N1[0]..N1[3]
Sets N1 modulus according to this table. These bits are set to implement
a divide-by-four on power-up.
N1[3]
0
0
0
0
0
0
0
0
1
1
1
1
N1[2]
0
0
0
0
1
1
1
1
X
X
X
X
N1[1]
0
0
1
1
0
0
1
1
0
0
1
1
N1[0]
0
1
0
1
0
1
0
1
0
1
0
1
RATIO
3
4
4
5
6
8
8
10
12
16
16
20
5
RESERVED
Must be set to zero.
6
JAMPLL
Tristates phase detector outputs, resets phase detector logic, and resets
R, A, M, and N2 counters.
7
DACRST
Set to zero for normal operations. When set to one, the CLK+ output is
kept high and the CLK- output is kept low. (All other device functions are
unaffected.) When returned to zero, the CLK+ and CLK- outputs will
resume toggling on a rising edge of the LD output (+/1 CLK period).
To initiate a RAMDAC reset sequence, simply write a one to this register
bit followed by a zero.
8
SELXTAL
When set to logic 1, passes the reference frequency to the post-scaler.
9
ALTLOOP
Controls substitution of N1 and N2 dividers into feedback loop of PLL.
When this bit is a logic 1, the N1 and N2 dividers are used.
10 SCEN
VRAM shift clock enable bit. When logic 1, the BLANK pin can be used
to disable the LD/N2 output.
11
EXTFBKEN
External PLL feedback select. When logic 1, the EXTFBK pin is used for
the phase-frequency detector feedback input.
12
PDRSTEN
Phase detector reset enable control bit. When this bit is set, a high level
on the BLANK input will disable PLL locking. See LINE-LOCKED
CLOCK GENERATION section for more details on the operation of
this function.
11

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