PDF KM416S1021C Data sheet ( Hoja de datos )

Número de pieza	KM416S1021C
Descripción	512K x 16-Bit x 2-Bank SDRAM
Fabricantes	Samsung Semiconductor
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No Preview Available ! KM416S1021C Preliminary CMOS SDRAM 512K x 16Bit x 2 Banks Synchronous DRAM with SSTL interface FEATURES • JEDEC standard 3.3V power supply • SSTL_3 (Class II) compatible with multiplexed address • Dual banks operation • MRS cycle with address key programs - CAS latency (2 & 3) - Burst length (1, 2, 4, 8 & Full page) - Burst type (Sequential & Interleave) • All inputs are sampled at the positive going edge of the system clock. • Burst read single-bit write operation • DQM for masking • Auto & self refresh • 64ms refresh period (4K cycle) FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION The KM416S1021C is 16,777,216 bits synchronous high data rate Dynamic RAM organized as 2 x 524,288 words by 16 bits, fabricated with SAMSUNG′s high performance CMOS technol- ogy. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance mem- ory system applications. ORDERING INFORMATION Part No. Max Freq. Interface Package KM416S1021CT-G7 KM416S1021CT-GS KM416S1021CT-G8 143MHz 100MHz(CL=2) 125MHz SSTL_3 (Class II) 54 TSOP(II) * KM416S1021CT-GS : CL=2 only Bank Select Data Input Register LWE LDQM CLK ADD 512K x 16 512K x 16 Column Decoder DQi LCKE LRAS LCBR LWE LCAS Latency & Burst Length Programming Register LWCBR LDQM www.datasheeCtL4K u.cCKoE m CS Timing Register RAS CAS WE L(U)DQM * Samsung Electronics reserves the right to change products or specification without notice. REV. 1. May '98 1 page KM416S1021C Preliminary CMOS SDRAM AC OPERATING TEST CONDITIONS(VDD = 3.3V ± 0.3V, 3.43V ± 0.5%, TA = 0 to 70°C) Parameter Input reference voltage Input signal maximum peak swing Inout signal minimum slew rate AC input levels (Vih/Vil) Input timing measurement reference level Output timing measurement reference level Output load condition Value 0.45 * VDDQ 2.0 1.0 VREF+0.4/VREF-0.4 VREF Vtt See Fig. 1 Unit V V V/ns V V V Vtt = 0.45 * VDDQ Output Z0 = 50Ω 50Ω VREF = 0.45 * VDDQ CLOAD=30pF (Fig. 1) Output load circuit OPERATING AC PARAMETER(AC operating conditions unless otherwise noted) Parameter Symbol Row active to row active delay RAS to CAS delay Row precharge time Row active time Row cycle time Last data in to new col. address delay Last data in to row precharge Last data in to burst stop Col. address to col. address delay Number of valid output data tRRD(min) tRCD(min) tRP(min) tRAS(min) tRAS(max) tRC(min) tCDL(min) tRDL(min) tBDL(min) tCCD(min) CAS latency=3 CAS latency=2 -7 14 21 21 49 70 2 1 Version -S 20 20 20 50 100 70 1 1 1 1 - 1 -8 16 24 24 56 80 2 1 Unit ns ns ns ns us ns CLK CLK CLK CLK ea Note 1 1 1 1 1 2 2 2 3 4 Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. REV. 1. May '98 5 Page

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