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PDF TE28F400B3xxx Data sheet ( Hoja de datos )

Número de pieza TE28F400B3xxx
Descripción (TE28F Series) SMART 3 ADVANCED BOOT BLOCK 4-8-16-32-MBIT FLASH MEMORY FAMILY
Fabricantes Intel 
Logotipo Intel Logotipo



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PRELIMINARY
SMART 3 ADVANCED BOOT BLOCK
4-, 8-, 16-, 32-MBIT
FLASH MEMORY FAMILY
28F400B3, 28F800B3, 28F160B3, 28F320B3
28F008B3, 28F016B3, 28F032B3
n Flexible SmartVoltage Technology
2.7 V–3.6 V Read/Program/Erase
12 V VPP Fast Production
Programming
n 2.7 V or 1.65 V I/O Option
Reduces Overall System Power
n High Performance
2.7 V–3.6 V: 90 ns Max Access Time
3.0 V–3.6 V: 80 ns Max Access Time
n Optimized Block Sizes
Eight 8-KB Blocks for Data,
Top or Bottom Locations
Up to Sixty-Three 64-KB Blocks for
Code
n Block Locking
VCC-Level Control through WP#
n Low Power Consumption
10 mA Typical Read Current
n Absolute Hardware-Protection
VPP = GND Option
VCC Lockout Voltage
n Extended Temperature Operation
–40 °C to +85 °C
n Flash Data Integrator Software
Flash Memory Manager
System Interrupt Manager
Supports Parameter Storage,
Streaming Data (e.g., Voice)
n Automated Program and Block Erase
Status Registers
n Extended Cycling Capability
Minimum 100,000 Block Erase
Cycles Guaranteed
n Automatic Power Savings Feature
Typical ICCS after Bus Inactivity
n Standard Surface Mount Packaging
48-Ball µBGA* Package
48-Lead TSOP Package
40-Lead TSOP Package
n Footprint Upgradeable
Upgrade Path for 4-, 8-, 16-, and 32-
Mbit Densities
n ETOX™ VI (0.25 µ) Flash Technology
The Smart 3 Advanced Boot Block, manufactured on Intel’s latest 0.25 µ technology, represents a feature-
rich solution at overall lower system cost. Smart 3 flash memory devices incorporate low voltage capability
(2.7 V read, program and erase) with high-speed, low-power operation. Several new features have been
added, including the ability to drive the I/O at 1.65 V, which significantly reduces system active power and
interfaces to 1.65 V controllers. A new blocking scheme enables code and data storage within a single
device. Add to this the Intel-developed Flash Data Integrator (FDI) software, and you have a cost-effective,
monolithic code plus data storage solution. Smart 3 Advanced Boot Block products will be available in 40-
lead and 48-lead TSOP and 48-ball µBGA* packages. Additional information on this product family can be
obtained by accessing Intel’s WWW page: http://www.intel.com/design/flash.
July 1998
Order Number: 290580-005

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TE28F400B3xxx pdf
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SMART 3 ADVANCED BOOT BLOCK
1.0 INTRODUCTION
This datasheet contains the specifications for the
Advanced Boot Block flash memory family, which is
optimized for low power, portable systems. This
family of products features 1.65 V–2.5 V or 2.7 V–
3.6 V I/Os and a low VCC/VPP operating range of
2.7 V–3.6 V for read, program, and erase
operations. In addition this family is capable of fast
programming at 12 V. Throughout this document,
the term “2.7 V” refers to the full voltage range
2.7 V–3.6 V (except where noted otherwise) and
“VPP = 12 V” refers to 12 V ±5%. Section 1.0 and
2.0 provide an overview of the flash memory family
including applications, pinouts and pin descriptions.
Section 3.0 describes the memory organization and
operation for these products. Sections 4.0 and 5.0
contain the operating specifications. Finally,
Sections 6.0 and 7.0 provide ordering and other
reference information.
1.1 Smart 3 Advanced Boot Block
Flash Memory Enhancements
The Smart 3 Advanced Boot Block flash memory
features
Enhanced blocking for easy segmentation of
code and data or additional design flexibility
Program Suspend to Read command
VCCQ input of 1.65 V–2.5 V on all I/Os. See
Figures 1 through 4 for pinout diagrams and
VCCQ location
Maximum program and erase time specification
for improved data storage.
Feature
Table 1. Smart 3 Advanced Boot Block Feature Summary
28F008B3, 28F016B3, 28F400B3(2), 28F800B3,
28F032B3(1)
28F160B3, 28F320B3
Reference
VCC Read Voltage
2.7 V– 3.6 V
Section 4.2, 4.4
VCCQ I/O Voltage
1.65 V–2.5 V or 2.7 V– 3.6 V
Section 4.2, 4.4
VPP Program/Erase Voltage
2.7 V– 3.6 V or 11.4 V– 12.6 V
Section 4.2, 4.4
Bus Width
8-bit
16 bit
Table 3
Speed
80 ns, 90 ns, 100 ns, 110 ns
Section 4.5
Memory Arrangement
1024 Kbit x 8 (8 Mbit),
2048 Kbit x 8 (16 Mbit),
4096 Kbit x 8 (32 Mbit)
256 Kbit x 16 (4 Mbit),
512 Kbit x 16 (8 Mbit),
1024 Kbit x 16 (16 Mbit)
2048 Kbit x 16 (32 Mbit)
Section 2.2
Blocking (top or bottom)
Eight 8-Kbyte parameter blocks and
Seven 64-Kbyte blocks (4-Mbit) or
Fifteen 64-Kbyte blocks (8-Mbit) or
Thirty-one 64-Kbyte main blocks (16-Mbit)
Sixty-three 64-Kbyte main blocks (32-Mbit)
Section 2.2
Appendix D
Locking
WP# locks/unlocks parameter blocks
All other blocks protected using VPP
Section 3.3
Table 8
Operating Temperature
Extended: –40 °C to +85 °C
Section 4.2, 4.4
Program/Erase Cycling
100,000 cycles
Section 4.2, 4.4
Packages
40-lead TSOP(1), 48-Ball 48-Lead TSOP, 48-Ball Figure 3, Figure 4
µBGA* CSP(2)
µBGA CSP(2)
NOTES:
1. 4-Mbit and 32-Mbit density not available in 40-lead TSOP.
2. 4-Mbit density not available in µBGA* CSP.
PRELIMINARY
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TE28F400B3xxx arduino
E
SMART 3 ADVANCED BOOT BLOCK
Symbol
VCCQ
VCC
VPP
GND
NC
Table 2. Smart 3 Advanced Boot Block Pin Descriptions (Continued)
Type
Name and Function
INPUT
OUTPUT VCC: Enables all outputs to be driven to 1.8 V – 2.5 V while
the VCC is at 2.7 V–3.3 V. If the VCC is regulated to 2.7 V–2.85 V, VCCQ
can be driven at 1.65 V–2.5 V to achieve lowest power operation (see
Section 4.4, DC Characteristics.
This input may be tied directly to VCC (2.7 V–3.6 V).
DEVICE POWER SUPPLY: 2.7 V–3.6 V
PROGRAM/ERASE POWER SUPPLY: Supplies power for program
and erase operations. VPP may be the same as VCC (2.7 V–3.6 V) for
single supply voltage operation. For fast programming at manufacturing,
11.4 V–12.6 V may be supplied to VPP. This pin cannot be left floating.
Applying 11.4 V–12.6 V to VPP can only be done for a maximum of 1000
cycles on the main blocks and 2500 cycles on the parameter blocks.
VPP may be connected to 12 V for a total of 80 hours maximum (see
Section 3.4 for details).
VPP < VPPLK protects memory contents against inadvertent or
unintended program and erase commands.
GROUND: For all internal circuitry. All ground inputs must be
connected.
NO CONNECT: Pin may be driven or left floating.
2.2 Block Organization
The Smart 3 Advanced Boot Block is an
asymmetrically-blocked architecture that enables
system integration of code and data within a single
flash device. Each block can be erased
independently of the others up to 100,000 times.
For the address locations of each block, see the
memory maps in Appendix D.
2.2.1
PARAMETER BLOCKS
The Smart 3 Advanced Boot Block flash memory
architecture includes parameter blocks to facilitate
storage of frequently updated small parameters
(e.g., data that would normally be stored in an
EEPROM). By using software techniques, the word-
rewrite functionality of EEPROMs can be emulated.
Each device contains eight parameter blocks of
8-Kbytes/4-Kwords (8192 bytes/4,096 words) each.
2.2.2
MAIN BLOCKS
After the parameter blocks, the remainder of the
array is divided into equal size main blocks (65,536
bytes / 32,768 words) for data or code storage. The
4-Mbit device contains seven main blocks; 8-Mbit
device contains fifteen main blocks; 16-Mbit flash
has thirty-one main blocks; 32-Mbit has sixty-three
main blocks.
3.0 PRINCIPLES OF OPERATION
Flash memory combines EEPROM functionality
with in-circuit electrical program and erase
capability. The Smart 3 Advanced Boot Block flash
memory family utilizes a Command User Interface
(CUI) and automated algorithms to simplify program
and erase operations. The CUI allows for 100%
CMOS-level control inputs and fixed power supplies
during erasure and programming.
PRELIMINARY
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