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PDF CC2420 Data sheet ( Hoja de datos )

Número de pieza CC2420
Descripción First Single-chip 2.4 GHZ Ieee 802.15.4 Compliant And Zigbeetm Ready RF Transceiver
Fabricantes Chipcon 
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SmartRF ® CC2420
CC2420
2.4 GHz IEEE 802.15.4 / Zigbee RF Transceiver
Applications
2.4 GHz IEEE 802.15.4 systems
ZigBee systems
Consumer Electronics
Product Description
The CC2420 is a true single-chip 2.4 GHz
IEEE 802.15.4 compliant RF transceiver
designed for low-power and low-voltage
wireless applications. CC2420 includes a
digital direct sequence spread spectrum
baseband modem providing a spreading
gain of 9 dB and an effective datarate of
250 kbps.
The CC2420 is a low-cost, highly integrated
solution for robust wireless communication
in the 2.4 GHz unlicensed ISM band. It
complies with world-wide regulations
covered by EN 300 440 (Europe), CFR47
Part 15 (US) and ARIB STD-T-66 (Japan).
The CC2420 provides extensive hardware
support for packet handling, data
buffering, burst transmissions, data
encryption, data authentication, clear
channel assessment, link quality indication
and packet timing information. These
features reduce the load on the host
Industrial Control
Home/building automation
PC peripherals
controller and allow CC2420 to interface
low-cost microcontrollers.
The configuration interface and transmit /
receive FIFOs of CC2420 are accessed via
a SPI interface. In a typical application
CC2420 will be used together with a
microcontroller and a few external passive
components.
CC2420 is based on Chipcon’s SmartRF®-
03 technology in 0.18 µm CMOS.
Key Features
True single-chip 2.4 GHz IEEE
No external RF switch / filter needed
802.15.4 compliant RF transceiver
I/Q low-IF receiver
with baseband modem and MAC
I/Q direct upconversion transmitter
support
Very few external components
DSSS baseband modem with 2
MChips/s and 250 kbps effective data
128 (RX) + 128 (TX) byte data
buffering
rate.
Suitable for both RFD and FFD
moperation
oLow current consumption (RX: 19.7
.cmA, TX: 17.4 mA)
uLow supply voltage (2.1 – 3.6 V) with
t4integrated voltage regulator
eLow supply voltage (1.6 – 2.0 V) with
eexternal voltage regulator
hProgrammable output power
Digital RSSI / LQI support
Hardware MAC encryption (AES-128)
Battery monitor
QLP-48 package, 7x7 mm
Complies with EN 300 440 and FCC
CFR-47 part 15, ARIB STD-T-66
Powerful and flexible development
tools available
tasThis document contains information on a pre-production product. Specifications and information herein are subject to
change without notice.
www.da Chipcon AS SmartRF® CC2420 Preliminary Datasheet (rev 1.0), 2003-11-17
Page 1 of 85

1 page




CC2420 pdf
SmartRF ® CC2420
SHR
SPI
TBD
T/R
TX
VCO
VGA
- Synchronisation Header
- Serial Peripheral Interface
- To Be Decided / To Be Defined
- Transmit / Receive
- Transmit
- Voltage Controlled Oscillator
- Variable Gain Amplifier
References
[1] IEEE std. 802.15.4/D18 - 2003: Wirelesss Medium Access Control (MAC)
and Physical Layer (PHY) specifications for Low Rate Wireless Personal
Area Networks (LR-WPANs)
http://www.ieee802.org/15/pub/TG4.html
[2] NIST FIPS Pub 197: Advanced Encryption Standard (AES), Federal
Information Processing Standards Publication 197, US Department of
Commerce/N.I.S.T., November 20014. Available from the NIST website.
http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf
[3] R. Housley, D. Whiting, N. Ferguson, Counter with CBC-MAC (CCM),
submitted to NIST, June 3, 2002. Available from the NIST website.
http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf
Chipcon AS SmartRF® CC2420 Preliminary Datasheet (rev 1.0), 2003-11-17
Page 5 of 85

5 Page





CC2420 arduino
SmartRF ® CC2420
Parameter
Phase noise
Min.
Typ.
109
117
117
117
Max.
Unit
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Condition / Note
Unmodulated carrier
At ±1 MHz offset from carrier
At ±2 MHz offset from carrier
At ±3 MHz offset from carrier
At ±5 MHz offset from carrier
PLL loop bandwidth
PLL lock time (RX / TX turnaround
time)
50 kHz
192 µs
Digital Inputs/Outputs
Logic "0" input voltage
0
0.3* V
DVDD
Signal levels are referred to the
voltage level at the pin DVDD3.3
Logic "1" input voltage
0.7*
DVDD
DVDD V
Logic "0" output voltage
Logic "1" output voltage
Logic "0" input current
0
2.5
NA
0.4 V
VDD V
1 µA
Output current 8 mA,
3.3 V supply voltage
Output current 8 mA,
3.3 V supply voltage
Input signal equals GND
Logic "1" input current
FIFO setup time
FIFO hold time
NA
20
10
1 µA Input signal equals VDD
ns TX un-buffered mode, minimum
time FIFO must be ready before
the positive edge of FIFOP
ns TX un-buffered mode, minimum
time FIFO must be held after the
positive edge of FIFOP
Serial interface pins (SCLK, SI, SO
and CSn) timing specification
See Table 4 on page 24
Voltage Regulator
Input Voltage
Output Voltage
Quiescent current
Startup time
2.1 3.0
1.7 1.8
13 20
0.3
3.6 V
1.9 V
29 µA
0.6 ms
On the VREG_IN pin
On the VREG_OUT pin
No current drawn from the
VREG_OUT pin. Min and max
numbers include 2.1 through 3.6
V input voltage
Chipcon AS SmartRF® CC2420 Preliminary Datasheet (rev 1.0), 2003-11-17
Page 11 of 85

11 Page







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