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PDF IC80C31 Data sheet ( Hoja de datos )
| Número de pieza | IC80C31 | |
| Descripción | (IC80C31 / IC80C51) CMOS SINGLE CHIP 8-BIT MICROCONTROLLER | |
| Fabricantes | Integrated Circuit Solution | |
| Logotipo |  |
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IIICCC88800CC05311C51
IC80C31
CMOS SINGLE CHIP
8-BIT MICROCONTROLLER
FEATURES
• 80C51 based architecture
• 4K x 8 ROM (IC80C51 only)
• 128 x 8 RAM
• Two 16-bit Timer/Counters
• Full duplex serial channel
• Boolean processor
• Four 8-bit I/O ports, 32 I/O lines
• Memory addressing capability
– 64K ROM and 64K RAM
• Program memory lock
– Encrypted verify (32 bytes)
– Lock bits (2)
• Power save modes:
– Idle and power-down
• Six interrupt sources
• Most instructions execute in 0.3 µs
• CMOS and TTL compatible
• Maximum speed: 40 MHz @ Vcc = 5V
• Packages available:
– 40-pin DIP
– 44-pin PLCC
– 44-pin PQFP
GENERAL DESCRIPTION
The ICSI IC80C51 and IC80C31 are high-performance
microcontroller fabricated using high-density CMOS
technology. The CMOS IC80C51/31 is functionally
compatible with the industry standard 80C51/31
microcontrollers.
The IC80C51/31 is designed with 4K x 8 ROM (IC80C51
only); 128 x 8 RAM; 32 programmable I/O lines; a serial I/
O port for either multiprocessor communications, I/O
expansion or full duplex UART; two 16-bit timer/counters;
an six-source, two-priority-level, nested interrupt structure;
and an on-chip oscillator and clock circuit. The IC80C51/31
can be expanded using standard TTL compatible memory.
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
RxD/P3.0
TxD/P3.1
INT0/P3.2
INT1/P3.3
T0/P3.4
T1/P3.5
WR/P3.6
RD/P3.7
XTAL2
XTAL1
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 VCC
39 P0.0/AD0
38 P0.1/AD1
37 P0.2/AD2
36 P0.3/AD3
35 P0.4/AD4
34 P0.5/AD5
33 P0.6/AD6
32 P0.7/AD7
31 EA
30 ALE
29 PSEN
28 P2.7/A15
27 P2.6/A14
26 P2.5/A13
25 P2.4/A12
24 P2.3/A11
23 P2.2/A10
22 P2.1/A9
21 P2.0/A8
Figure 1. IC80C51/31 Pin Configuration: 40-pin DIP
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
MC001-0B
1
1 page  
IC80C51
IC80C31
Table 1. Detailed Pin Description
Symbol
ALE
PDIP
30
PLCC
33
PQFP I/O
27 I/O
EA 31 35 29 I
P0.0-P0.7 39-32
43-36
37-30 I/O
P1.0-P1.7 1-8
2-9 40-44 I/O
1-3
P2.0-P2.7 21-28
24-31
18-25 I/O
Name and Function
Address Latch Enable: Output pulse for latching the low byte
of the address during an access to the external memory. In
normal operation, ALE is emitted at a constant rate of 1/6 the
oscillator frequency, and can be used for external timing or
clocking. Note that one ALE pulse is skipped during each
access to external data memory.
External Access enable: EA must be externally held low to
enable the device to fetch code from external program memory
locations 0000H to FFFFH. If EA is held high, the device
executes from internal program memory unless the program
counter contains an address greater than internal ROM seze.
Port 0: Port 0 is an 8-bit open-drain, bidirectional I/O port. Port
0 pins that have 1s written to them float and can be used as high-
impedance inputs. Port 0 is also the multiplexed low-order
address and data bus during accesses to external program and
data memory. In this application, it uses strong internal pullups
when emitting 1s.
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal
pullups. Port 1 pins that have 1s written to them are pulled high
by the internal pullups and can be used as inputs. As inputs, Port
1 pins that are externally pulled low will source current because
of the internal pullups. (See DC Characteristics: IIL). The Port 1
output buffers can sink/source four TTL inputs.
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal
pullups. Port 2 pins that have 1s written to them are pulled high
by the internal pullups and can be used as inputs. As inputs, Port
2 pins that are externally pulled low will source current because
of the internal pullups. (See DC Characteristics: IIL). Port 2 emits
the high order address byte during fetches from external pro-
gram memory and during accesses to external data memory
that used 16-bit addresses (MOVX @ DPTR). In this application,
Port 2 uses strong internal pullups when emitting 1s. During
accesses to external data memory that use 8-bit addresses
(MOVX @ Ri [i = 0, 1]), Port 2 emits the contents of the P2
Special Function Registers.
Integrated Circuit Solution Inc.
MC001-0B
5
5 Page 
IC80C51
IC80C31
The detail description of each bit is as follows:
PSW:
Program Status Word. Bit Addressable.
765 4 3 2
CY AC F0 RS1 RS0 OV
10
—P
Register Description:
CY PSW.7 Carry flag.
AC PSW.6 Auxiliary carry flag.
F0 PSW.5 Flag 0 available to the user for
general purpose.
RS1 PSW.4 Register bank selector bit 1.(1)
RS0 PSW.3 Register bank selector bit 0.(1)
OV PSW.2 Overflow flag.
— PSW.1 Usable as a general purpose flag
P PSW.0 Parity flag. Set/Clear by hardware each
instruction cycle to indicate an odd/even
number of “1” bits in the accumulator.
Note:
1. The value presented by RS0 and RS1 selects the corre-
sponding register bank.
RS1 RS0 Register Bank
Address
0 0 0 00H-07H
0 1 1 08H-0FH
1 0 2 10H-17H
1 1 3 18H-1FH
PCON:
Power Control Register. Not Bit Addressable.
7 6 5 4 3 2 10
SMOD — — — GF1 GF0 PD IDL
Register Description:
SMOD
Double baud rate bit. If Timer 1 is used to generate
baud rate and SMOD=1, the baud rate is doubled
when the serial port is used in modes 1, 2, or 3.
— Not implemented, reserve for future use.(1)
— Not implemented, reserve for future use.(1)
— Not implemented, reserve for future use.(1)
GF1 General purpose flag bit.
GF0 General purpose flag bit.
PD Power-down bit. Setting this bit activates power-
down mode.
IDL Idle mode bit. Setting this bit activates idle mode.
operation in the IC80C51/31. If 1s are written to
PD and IDL at the same time, PD takes precedence.
Note:
1. User software should not write 1s to reserved bits. These
bits may be used in future products to invoke new features.
IE:
Interrupt Enable Register. Bit Addressable.
7 6 5 4 3 2 10
EA — — ES ET1 EX1 ET0 EX0
Register Description:
EA IE.7
Disable all interrupts. If EA=0, no interrupt
will be acknowledged. If EA=1, each
interrupt source is individually enabled
or disabled by setting or clearing its
enable bit.
— IE.6
Not implemented, reserve for future use.
(5)
— IE.5
Not implemented, reserve for future use.
(5)
ES IE.4
Enable or disable the serial port interrupt.
ET1 IE.3
Enable or disable the Timer 1 overflow
interrupt.
EX1 IE.2
Enable or disable External Interrupt 1.
ET0 IE.1
Enable or disable the Timer 0 overflow
interrupt.
EX0 IE.0
Enable or disable External Interrupt 0.
Note: To use any of the interrupts in the 80C51 Family, the
following three steps must be taken:
1. Set the EA (enable all) bit in the IE register to 1.
2. Set the coresponding individual interrupt enable bit in
the IE register to 1.
3. Begin the interrupt service routine at the corresponding
Vector Address of that interrupt (see below).
Interrupt Source
IE0
TF0
IE1
TF1
RI & TI
Vector Address
0003H
000BH
0013H
001BH
0023H
4. In addition, for external interrupts, pins INT0 and INT1
(P3.2 and P3.3) must be set to 1, and depending on
whether the interrupt is to be level or transition activated,
bits IT0 or IT1 in the TCON register may need to be set to
0 or 1.
ITX = 0 level activated (X = 0, 1)
ITX = 1 transition activated
5. User software should not write 1s to reserved bits. These
bits may be used in future products to invoke new features.
Integrated Circuit Solution Inc.
MC001-0B
11
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