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PDF GM71V16163C Data sheet ( Hoja de datos )
| Número de pieza | GM71V16163C | |
| Descripción | (GM71VS16163CL / GM71V16163C) 1M x 16-Bit CMOS DRAM | |
| Fabricantes | Hynix Semiconductor | |
| Logotipo |  |
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GM71V16163C
GM71VS16163CL
1,048,576 WORDS x 16 BIT
CMOS DYNAMIC RAM
Description
The GM71V(S)16163C/CL is the new generation
dynamic RAM organized 1,048,576 x 16 bit.
GM71V(S)16163C/CL has realized higher density,
higher performance and various functions by utilizing
advanced CMOS process technology. The
GM71V(S)16163C/CL offers Extended Data
out(EDO) Mode as a high speed access mode.
Multplexed address inputs permit the
GM71V(S)16163C/CL to be packaged in standard
400 mil 42pin plastic SOJ, and standard 400mil
44(50)pin plastic TSOP II. The package size provides
high system bit densities and is compatible with
widely available automated testing and insertion
equipment.
Pin Configuration
Features
* 1,048,576 Words x 16 Bit Organization
* Extended Data Out Mode Capability
* Single Power Supply (3.3V+/-0.3V)
* Fast Access Time & Cycle Time (Unit: ns)
t t t tRAC CAC RC
HPC
GM71V(S)16163C/CL-5 50 13 84 20
GM71V(S)16163C/CL-6 60 15 104 25
GM71V(S)16163C/CL-7 70 18 124 30
GM71V(S)16163C/CL-8 80 20 144 35
* Low Power
Active : 396/360/324/288mW (MAX)
Standby : 7.2mW (MAX)
0.83mW (L-series : MAX)
* RAS Only Refresh, CAS before RAS Refresh,
Hidden Refresh Capability
* All inputs and outputs TTL Compatible
* 4096 Refresh Cycles/64ms
* 4096 Refresh Cycles/128ms (L-series)
* Self Refresh Operation (L-version)
* Battery Back Up Operation (L-series)
* 2 CAS byte Control
42 SOJ
44(50) TSOP II
VCC 1
42 VSS
I/O0 2
41 I/O15
I/O1 3
40 I/O14
I/O2 4
39 I/O13
I/O3 5
38 I/O12
VCC 6
37 VSS
I/O4 7
36 I/O11
I/O5 8
35 I/O10
I/O6 9
34 I/O9
I/O7 10
33 I/O8
NC 11
32 NC
NC 12
31 LCAS
WE 13
30 UCAS
RAS 14
29 OE
A11 15
A10 16
mA0 17
oA1 18
.cA2 19
A3 20
uVCC 21
www.datasheet4Rev 0.1 / Apr’01
28 A9
27 A8
26 A7
25 A6
24 A5
23 A4
22 VSS
(Top View)
VCC 1
I/O0 2
I/O1 3
I/O2 4
I/O3 5
VCC 6
I/O4 7
I/O5 8
I/O6 9
I/O7 10
NC 11
NC 15
NC 16
WE 17
RAS 18
A11 19
A10 20
A0 21
A1 22
A2 23
A3 24
VCC 25
50 VSS
49 I/O15
48 I/O14
47 I/O13
46 I/O12
45 VSS
44 I/O11
43 I/O10
42 I/O9
41 I/O8
40 NC
36 NC
35 LCAS
34 UCAS
33 OE
32 A9
31 A8
30 A7
29 A6
28 A5
27 A4
26 VSS
1 page  
Capacitance (VCC = 3.3V+/-0.3V, TA = 25C)
Symbol
Parameter
GM71V16163C
GM71VS16163CL
Min Max Unit Note
CI1 Input Capacitance (Address)
- 5 pF 1
CI2 Input Capacitance (Clocks)
- 7 pF 1
CI/O Output Capacitance (Data-In/Out)
- 7 pF 1, 2
Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. CAS = VIH to disable DOUT.
AC Characteristics (VCC = 3.3V+/-0.3V, TA = 0 ~ +70C, Vss = 0V) Note 1, 2, 18, 19, 20
Test Conditions
Input rise and fall times : 2 ns
Input timing reference levels : 0.8V, 2.0V
Output load : 1TTL gate + CL (100 pF)
(Including scope and jig)
Output timing reference levels : 0.8V, 2.0V
Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters)
Symbol
Parameter
GM71V(S)16163 GM71V(S)16163 GM71V(S)16163 GM71V(S)16163
C/CL-5
C/CL-6
C/CL-7
C/CL-8
Unit Note
Min Max Min Max Min Max Min Max
tRC Random Read or Write Cycle Time
84 - 104 - 124 - 144 - ns
tRP RAS Precharge Time
30 - 40 - 50 - 60 - ns
tCP CAS Precharge Time
8 - 10 - 13 - 15 - ns
tRAS RAS Pulse Width
tCAS CAS Pulse Width
tASR Row Address Set up Time
tRAH Row Address Hold Time
tASC Column Address Set-up Time
tCAH Column Address Hold Time
tRCD RAS to CAS Delay Time
tRAD RAS to Column Address Delay Time
tRSH RAS Hold Time
tCSH CAS Hold Time
tCRP CAS to RAS Precharge Time
tOED OE to DIN Delay Time
tDZO OE Delay Time from DIN
tDZC CAS Delay Time from DIN
tT TransitionTime (Rise and Fall)
50 10,000
8 10,000
0-
8-
0-
8-
12 37
10 25
10 -
35 -
5-
13 -
0-
0-
2 50
60 10,000 70 10,000 80 10,000 ns
10 10,000 13 10,000 15 10,000 ns
0-
0-
0 - ns
10 - 10 - 10 - ns
0-
10 -
14 45
12 30
0-
13 -
14 52
12 35
0 - ns
15 - ns
20 60 ns
15 40 ns
13 -
40 -
13 -
45 -
18 - ns
50 - ns
5-
5-
5 - ns
15 - 18 - 20 - ns
0-
0-
2 50
0-
0-
2 50
0 - ns
0 - ns
2 50 ns
21
21
3
4
23
22
5
6
6
7
Rev 0.1 / Apr’01
5 Page 
GM71V16163C
GM71VS16163CL
21. tASC, tCAH, tRCS, tWCS,tWCH,tCSR and tRPC are determined by the earlier falling edge of UCAS
or LCAS.
22. tCRP,tCHR, tRCH, tACP and tCPW are determned by the later rising edge of UCAS or LCAS.
23. tCWL, tDH,tDS and tCSH should be satisfied by both UCAS and LCAS.
24. tCP is determined by that time the both UCAS and LCAS are high.
25. When output buffers are enabled once, sustain the low impedence state until valid data is
obtained.
When output buffer is turned on and off within a very short time, generally it causes large
VCC/VSS line noise, which causes to degrade VIH min/VIL max level.
26. Please do not use tRASS timing, 10us <= tRASS <=100us. During this period, the device is in
transition state from normal operation mode to self refresh mode. If tRASS >=100us, then
RAS precharge time should use tRPS instead of tRP.
27. If you use distributed CBR refresh within 15.6us inteval in normal read/write cycle, CBR
refresh should be executed within 15.6us immediately after exiting from and before entering
into self refresh mode.
28. If you use RAS only refresh or CBR burst refresh mode in normal read/write cycle,4096 or
1024 cycles of distributed CBR refresh with 15.6us interval should be executed within 64 or
16ms immediately after exiting from and before entering into the self refresh mode.
29. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from
self refresh mode, all memory cells need to be refreshed before re-entering the self refresh mode
again.
30. H or L (H: VIH(min) <= VIN <= VIH(max), L: VIL(min) <= VIN <= VIL(max))
Rev 0.1 / Apr’01
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet GM71V16163C.PDF ] | |
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