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PDF GM71VS65163AL Data sheet ( Hoja de datos )

Número de pieza GM71VS65163AL
Descripción (GM71VS65163AL / GM71V65163A) 4M x 16-Bit CMOS DRAM
Fabricantes Hynix Semiconductor 
Logotipo Hynix Semiconductor Logotipo



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No Preview Available ! GM71VS65163AL Hoja de datos, Descripción, Manual

LG Semicon Co.,Ltd.
GM71V65163A
GM71VS65163AL
4,196,304 WORDS x 16 BIT
CMOS DYNAMIC RAM
Description
Pin Configuration
The GM71V(S)65163A/AL is the new generation
dynamic RAM organized 4,196,304 words by 16
bits. The GM71V(S)65163A/AL utilizes advanced
CMOS Silicon Gate Process Technology as well as
advanced circuit techniques for wide operating
margins, both internally and to the system user.
System oriented features include single power supply
of 3.3V+/-10% tolerance, direct interfacing
capability with high performance logic families such
as Schottky TTL.
The GM71V(S)65163A/AL offers Extended Data
Out(EDO) Mode as a high speed access mode.
50 SOJ / TSOP ¥±
VCC
IO0
1
2
IO1 3
IO2 4
IO3 5
VCC 6
IO4 7
IO5 8
IO6 9
IO7 10
NC 11
VCC 12
Features
/WE 13
/RAS 14
* 4,196,304 Words x 16 Bit
* Extended Data Out (EDO) Mode Capability
* Fast Access Time & Cycle Time
(Unit: ns)
NC 15
NC 16
NC 17
NC 18
A0 19
tRAC tAA tCAC tRC
tHPC
A1 20
A2 21
GM71V(S)65163A/AL-5 50 25 13 90 20
GM71V(S)65163A/AL-6 60 30 15 110 25
A3 22
A4 23
A5 24
VCC 25
*Power dissipation
- Active : 720mW/648mW(MAX)
- Standby : 1.8 mW ( CMOS level : MAX )
0.54mW ( L-Version : MAX)
*EDO page mode capability
*Access time : 50ns/60ns (max)
*Refresh cycles
- RAS only Refresh
4096 cycles/64 §Â (GM71V65163A)
4096 cycles/128§Â (GM71VS65163AL)(L_Version)
*CBR & Hidden Refresh
4096 cycles/64 §Â (GM71V65163A)
m4096 cycles/128 §Â (GM71VS65163AL)( L-Version )
o*4 variations of refresh
.c-RAS-only refresh
u-CAS-before-RAS refresh
t4-Hidden refresh
-Self refresh (L-Version)
ee*Single Power Supply of 3.3V+/-10 % with a built-in VBB generator
www.datash*Battery Back Up Operation ( L-Version )
(Top View)
1
50 VSS
49 IO15
48 IO14
47 IO13
46 IO12
45 VSS
44 IO11
43 IO10
42 IO9
41 IO8
40 NC
39 VSS
38 /LCAS
37 /UCAS
36 /OE
35 NC
34 NC
33 NC
32 A11
31 A10
30 A9
29 A8
28 A7
27 A6
26 VSS

1 page




GM71VS65163AL pdf
LG Semicon
GM71V65163A
GM71VS65163AL
Read Cycles
Symbol
Parameter
tRAC Access Time from RAS
tCAC Access Time from CAS
tAA Access Time from Column Address
tOAC Access Time from OE
tRCS Read Command Set-up Time
tRCH Read Command Hold Time to CAS
tRRH Read Command Hold Time to RAS
tRAL Column Address to RAS Lead Time
tCAL Column Address to CAS Lead Time
tOFF Output Buffer Turn-off Delay Time from CAS
tOEZ Output Buffer Turn-off Delay Time from OE
tCDD CAS to DIN Delay Time
tRDD RAS to DIN Delay Time
tWDD
tOFR
tWEZ
WE to DIN Delay Time
Output Buffer Turn-off Delay Time from RAS
Output Buffer Turn-off Delay Time from WE
tOH Output Data Hold Time
tOHR Output Data Hold Time from RAS
tRCHR Read Command Hold Time from RAS
tOHO Output data hold time from OE
tCLZ CAS to Output in Low - Z
GM71V(S)65163A/AL-5 GM71V(S)65163A/AL-6
Unit
Min Max Min Max
Notes
- 50 - 60 §À 8,9
- 13 - 15 §À 9,10,17
- 25 - 30 §À 9,11,17
- 13 - 15 §À 9
0 - 0 - §À 21
0 - 0 - §À 12,22
0 - 0 - §À 12
25 - 30 - §À
15 - 18 - §À
- 13 - 15 §À 13,26
- 13 - 15 §À 13
13 - 15 - §À 5
13 - 15 - §À
13 - 15 - §À
- 13 - 15 §À 13,26
- 13 - 15 §À 13
3 - 3 - §À 26
3 - 3 - §À 26
50 - 60 - §À
3 - 3 - §À
0 - 0 - §À
5

5 Page





GM71VS65163AL arduino
LG Semicon
GM71V65163A
GM71VS65163AL
RAS
UCAS
LCAS
ADDRESS
WE
DIN
DOUT
tRC
tRAS
tRP
tRSH
tT
tRCD
tCAS
tCRP
tCSH
tASR
tRAH
ROW
tASC
tCAH
COLUMN
tWCS
tWCH
tDS
DIN
tDH
High-Z
* tWCS => tWCS (min)
FIGURE 2. EARLY WRITE CYCLE
11

11 Page







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