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PDF ST95040 Data sheet ( Hoja de datos )

Número de pieza ST95040
Descripción (ST950x0) 4K/2K/1K Serial SPI EEPROM with Positive Clock Strobe
Fabricantes ST Microelectronics 
Logotipo ST Microelectronics Logotipo



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No Preview Available ! ST95040 Hoja de datos, Descripción, Manual

ST95040
ST95020, ST95010
4K/2K/1K Serial SPI EEPROM with Positive Clock Strobe
1 MILLION ERASE/WRITE CYCLES
40 YEARS DATA RETENTION
SINGLE SUPPLY VOLTAGE
– 4.5V to 5.5V for ST950x0
– 2.5V to 5.5V for ST950x0W
SPI BUS COMPATIBLE SERIAL INTERFACE
2 MHz CLOCK RATE MAX
BLOCK WRITE PROTECTION
STATUS REGISTER
16 BYTE PAGE MODE
WRITE PROTECT
SELF-TIMED PROGRAMMING CYCLE
E.S.D.PROTECTION GREATER than 4000V
SUPPORTS POSITIVE CLOCK SPI MODES
8
1
PSDIP8 (B)
0.25mm Frame
8
1
SO8 (M)
150mil Width
Figure 1. Logic Diagram
DESCRIPTION
The ST950x0 is a family of Electrically Erasable
Programmable Memories (EEPROM) fabricated
with STMicroelectronics’s High Endurance Single
Polysilicon CMOS technology. Each memory is
accessed by a simple SPI bus compatible serial
interface. The bus signals are a serial clock input
(C), a serial data input (D) and a serial data output
(Q).
Table 1. Signal Names
C Serial Clock
D Serial Data Input
Q Serial Data Output
S Chip Select
W Write Protect
HOLD
Hold
VCC Supply Voltage
VSS Ground
VCC
D
C
S
W
HOLD
ST950x0
Q
VSS
AI01435B
June 1998
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ST95040 pdf
Figure 5. Block Diagram
ST95040, ST95020, ST95010
HOLD
W
S
C
D
Q
Control Logic
High Voltage
Generator
I/O Shift Register
Address Register
and Counter
Data
Register
Status
Block
Protect
16 Bytes
X Decoder
AI01272
During a write to the memory operation to the
memory array, all bits BP1, BP0, WEL, WIP are
valid and can be read. During a write to the status
register, only the bits WEL and WIP are valid and
can be read. The values of BP1 and BP0 read at
that time correspondto the previouscontents of the
status register.
The Write-In-Process (WIP) read-only bit indicates
whether the Memory is busy with a write operation.
When set to a ’1’ a write is in progress, when set to
a ’0’ no write is in progress.
The Write Enable Latch (WEL) read-only bit indi-
cates the status of the write enable latch. When set
to a ’1’ the latch is set, when set to a ’0’ the latch is
reset. The Block Protect (BP0 and BP1) bits indi-
cate the extent of the protection employed. These
bits are set by the user issuing the WRSR instruc-
tion. These bits are non-volatile.
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ST95040 arduino
Table 5. AC Measurement Conditions
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing
Reference Voltages
50ns
0.2VCC to 0.8VCC
0.3VCC to 0.7VCC
Output Load
CL = 100pF
Note that Output Hi-Z is defined as the point where data is no
longer driven.
ST95040, ST95020, ST95010
Figure 13. AC Testing Input Output Wavef.
0.8VCC
0.2VCC
0.7VCC
0.3VCC
AI00825
Table 6. Input Parameters (1) (TA = 25 °C, f = 2 MHz )
Symbol
Parameter
CIN Input Capacitance (D)
CIN Input Capacitance (other pins)
tLPF Input Signal Pulse Width Filtered Out
Note: 1. Sampled only, not 100% tested.
Min Max Unit
8 pF
6 pF
10 ns
Table 7. DC Characteristics
(TA = 0 to 70°C, –40 to 85°C or –40 to 125°C; VCC = 4.5V to 5.5V or 2.5V to 5.5V)
Symbol
Parameter
Test Condition
Min
ILI Input Leakage Current
ILO Output Leakage Current
Supply Current
ICC
C = 0.1 VCC/0.9 VCC ,
@ 2 MHz, Q = Open
C = 0.1 VCC/0.9 VCC ,
@ 2 MHz, Q = Open, Note 2
Supply Current (W series)
C = 0.1 VCC/0.9 VCC ,
@ 1 MHz, VCC = 2.5V,
Q = Open
Standby Current
ICC1
S = VCC, VIN = VSS or VCC
S = VCC, VIN = VSS or VCC,
Note 2
Standby Current (W series)
S = VCC, VIN = VSS or VCC,
VCC = 2.5V
VIL Input Low Voltage
VIH Input High Voltage
VOL (1)
Output Low Voltage
Output Low Voltage (W series)
IOL = 2mA
IOL = 2mA, Note 2
IOL = 1.5mA, VCC = 2.5V
– 0.3
0.7 VCC
VOH (1) Output High Voltage
IOH = –2mA
IOH = –2mA, Note 2
Output High Voltage (W series)
IOH = –0.4mA, VCC = 2.5V
Notes: 1. The device meets output requirements for both TTL and CMOS standards.
2. Test performed at –40 to 125°C temperature range, grade 3.
VCC –0.6
VCC –0.6
VCC –0.3
Max
±2
±2
2
2
1.5
50
50
25
0.3 VCC
VCC + 1
0.4
0.4
0.4
Unit
µA
µA
mA
mA
mA
µA
µA
µA
V
V
V
V
V
V
V
V
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