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PDF SAA128M4T27B Data sheet ( Hoja de datos )
| Número de pieza | SAA128M4T27B | |
| Descripción | 512M DDR SDRAM | |
| Fabricantes | SpecTek | |
| Logotipo |  |
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512Mb: x4, x8, x16
DDR SDRAM
DOUBLE DATA RATE
(DDR) SDRAM
FEATURES
• PC2100, PC2700 and PC3200 compatible
• VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V (For –6A & -
75A)
• VDD = +2.6V ±0.1V, VDDQ = +2.6V ±0.1V (For -5B)
• Bi-directional data strobe (DQS) transmitted/ received with
data, i.e. source-synchronous data capture (x16 has two:
LDQS and UDQS – one per byte)
• Internal, pipelined double-data-rate (DDR) architecture; two
data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-aligned
with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data (x16 has two: LDM
and UDM – one per byte)
• Programmable burst lengths: 2, 4, or 8
• Auto precharge option
• Auto Refresh
• Longer lead TSOP for improved reliability (OCPL)
• 2.5V I/O (SSTL_2 compatible)
• These devices are optimized for single rank DIMM
applications
Package Types:
66-pin Plastic TSOP, OCPL
(400 mil width, 0.65mm pin pitch)
60-ball (10mm x 12.5mm) FBGA
TW
FN
Timing – Cycle Time:
5ns @ CL=3 (PC3200 or DDR400B)
6ns @ CL = 2.5 (PC2700 or DDR333)
7.5ns @ CL = 2.5 (PC2100 or DDR266)
-5B
-6A
-75A
Part number example:
(For part numbers prior to December
2004, refer to page 12 for decoding.)
SAA64M8T27BV8TW-6A
PIN ASSIGNMENT (TOP VIEW)
66-PIN TSOP
Options:
Designation:
Family:
SpecTek Memory
SAA
Configuration:
128 Meg x 4 (32 Meg x 4 x 4 banks)
64 Meg x 8 (16 Meg x 8 x 4 banks)
32 Meg x 16 (8 Meg x 16 x 4 banks)
128M4
64M8
32M16
Design ID:
DDR2 512 Megabit Design
m(Call SpecTek Sales for details on
oavailability of “x” placeholders)
u.cVoltage and refresh:
t42.5V, Auto Refresh
e2.5V, Self or Auto Refresh
.datashePDF=09005aef80c1b136 / Source=09005aef80c1a8c0
512Mb: x4, x8, x16 DDR SDRAM
wwwRev: 11/24/2004
Tx7x
V8
R8
0
www.spectek.com
SpecTek reserves the right to change products or specifications
without notice. © 2003, 2004 SpecTek
1 page  
512Mb: x4, x8, x16
DDR SDRAM
CAPACITANCE (x16)
(For test conditions see note 53)
PARAMETER
Delta Input/Output Capacitance: DQ0 – DQ7, LDQS, LDM
Delta Input/Output Capacitance: DQ8-DQ15, UDQS, UDM
Delta Input Capacitance: Command and Address
Delta Input Capacitance: CK, CK#
Input/Output Capacitance: DQs, LDQS, UDQS, LDM, UDM
Input Capacitance: Command and Address
Input Capacitance: CK, CK#
Input Capacitance: CKE
SYMBOL
DCIOL
DCIOU
DCI1
DCI2
CIO
CI1
CI2
CI3
MIN
--
--
--
--
4.0
2.0
2.0
2.0
MAX
0.50
0.50
0.50
0.25
5.0
3.0
3.0
3.0
UNITS
pF
pF
pF
pF
pF
pF
pF
pF
NOTES
24
24
29
29
IDD SPECIFICATIONS AND CONDITIONS (x16)
(For test conditions see note 53)
PARAMETER/CONDITION
SYMBO -5B -6A -75 UNITS NOTES
OPERATING CURRENT: One bank; Active-Precharge; tRC = tRC (MIN); tCK =
tCK (MIN); DQ, DM, and DQS inputs changing once per clock cycle; Address and
L
IDD0
155 135 120
mA
22, 48
control inputs changing once every two clock cycles;
OPERATING CURRENT: One bank; Active-Read-Precharge; Burst = 2; tRC =
tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing
IDD1
185 160 145
mA
22, 48
once per clock cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: All
banks idle; Power-down mode; tCK = tCK(MIN); CKE=LOW;
Standard
‘V’ parts
IDD2P
10 10 10
mA
23, 32,
50
Self Refresh
IDD2P
63
5
mA 23, 32,
‘R’ parts
50
PRECHARGE FLOATING STANDBY CURRENT: CS# = HIGH; All banks idle;
tCK = tCK (MIN); CKE = HIGH; Address and other control inputs changing once
IDD2F
55 55 55
mA
51
per clock cycle. VIN = VREF for DQ, DQS, and DM
ACTIVE POWER-DOWN STANDBY CURRENT: One bank active; Power-down
IDD3P
45 35 25
mA
23, 32,
mode; tCK = tCK (MIN); CKE = LOW
50
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One bank; Active-
Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs
IDD3N
60 65 65
mA
22
changing twice per clock cycle; Address and other control inputs changing once per
clock cycle.
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank active;
Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT
IDD4R 210 190 180
mA
22, 48
= 0Ma
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank active;
Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ,
IDD4W 190 165 155
mA
22
DM, and DQS inputs changing twice per clock cycle
AUTO REFRESH CURRENT
tRC = tRFC (MIN)
IDD5
345 260 260
mA
22, 50
SELF REFRESH CURRENT (Part number ‘R’ only)
IDD6
65
4
mA
11
OPERATING CURRENT: Four bank interleaving READs (BL = 4) with auto
precharge, tRC = tRC (MIN); tCK = tRC (MIN); Address and control inputs change
IDD7
405 400 335
mA
22, 49
only during Active, READ, or WRITE commands.
PDF=09005aef80c1b136 / Source=09005aef80c1a8c0
512Mb: x4, x8, x16 DDR SDRAM
Rev: 11/24/2004
0
www.spectek.com
SpecTek reserves the right to change products or specifications
without notice. © 2003, 2004 SpecTek
5 Page 
512 Mb: x4, x8, x16
DDR SDRAM
60-Ball FBGA (10mm x 12.5mm)
NOTE:
All dimensions in millimeters.
PDF=09005aef80c1b136 / Source=09005aef80c1a8c0
512Mb: x4, x8, x16 DDR SDRAM
Rev: 11/24/2004
11
www.spectek.com
SpecTek reserves the right to change products or specifications
without notice. © 2003, 2004 SpecTek
11 Page | ||
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