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PDF DMC73C168 Data sheet ( Hoja de datos )
| Número de pieza | DMC73C168 | |
| Descripción | 8Bit Single Chip Microcontroller | |
| Fabricantes | Daewoo Semiconductor | |
| Logotipo |  |
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8Bit Single Chip Microcontroller
Table of Contents
1. INTRODUCTION
1.1 Key Features
2. DMC73C168 BLOCK DIAGRAM
3. PIN ASSIGNMENT AND DESCRIPTION
3.1 DMC73C168 Pin Assignment
3.2 Description
4. ARCHITECTURE
4.1 Register File (RF)
4.2 Peripheral File (PF)
4.3 Peripheral RAM File (PRF)
4.4 Stack Pointer (SP)
4.5 Status Register (ST)
4.6 Program Counter (PC)
4.7 Peripheral File Map
4.8 Interrupt and Reset Priorities
5. DESCRIPTION OF EACH FUNCTION
5.1 Input / Output Ports
5.2 Device Initialization
5.3 I/O Control Register
5.4 Interrupt Logic and External Interrupt
5.5 Programmable Timer / Event Counter
5.6 A/D Converter
5.7 PLL
5.8 IF Counter
5.9 Serial Communication I/O Ports : SIO1, SIO2
6. OTP DEVICE SPECIFICATION
6.1 Pin Assignment of OTP and OTP Programming Adapter Board
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DAEWOO ELECTRONICS CO., LTD.
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DMC73C168
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1 page  
8Bit Single Chip Microcontroller
2. DMC73C168 BLOCK DIAGRAM
5
DMC73C168
RESET
CE
(INT1)
Interrupt
Control
VDD ¡æ
VSS ¡æ
8 BIT
CPU
RAM
384 Byte
OSCIN
OSCOUT
TEST ¡æ
EO1 ¡ç
EO2 ¡ç
VCOL ¡æ
VCOH ¡æ
VREF ¡æ
VASS ¡æ
OSC
GEN
Peripheral
/Memory
Control
ROM
16 Kbyte
Phase Locked
Loop
INT4-0 EXT INT4
INT3 EXT INT3 PORT A
INT4-1 A/D CON
INT2 TIMER1 BEEP GEN
INT6 TIMER2 PORT E
INT5 SIO 1
INT7 SIO 2
PORT B
¡ê A0/FMIF
¡ê A1/AMIF
¡ê A2/AD1
¡ê A3/AD2
¡ê A4/ECI1
¡ê A5/ECI2
¡ê A6/INT4
¡ê A7/INT3
¡ê E0/SO1
¡ê E1/SI1
¡ê E2/SCLK1
¡ê E3/SO2
¡ê E4/SI2
¡ê E5/SCLK2
¡ê E6
¡ê E7/BEEP
¡ê B0/T1OUT
¡ê B1/T2OUT
PORT B ¡ê B2-B7
PORT C ¡ê C0-C7
PORT D ¡ê D0-D7
PORT F ¡ê F0-F7
H0-H7 ¡ê PORT H
PORT G ¡ê G0-G7
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DAEWOO ELECTRONICS CO., LTD.
5 Page 
8Bit Single Chip Microcontroller
11
DMC73C168
NAME PIN NO. I/O
FUNCTION DESCRIPTION
NC 78
No connection
PORT TYPE
RESET
80
I System reset request input port.
The reset pin must be held low for minimum of 5 internal
clock cycles to guarantee recognition by the device.
The dev ice initialization requires 15 machine cycles.
CE/INT1 79
I Device selection Signal input port.
External interrupt input port.
This port can be used as a Chip Enable input.
W hen activated, CPU resumes its operation from HALT
mode
Schimitt-
Tri gger-IN
4. ARCHITECTURE
The DMC73C168 has a maximum memory address space of 64K bytes and only the Single-Chip mode.
On-Chip memory spaces are configured as shown in Table 4.1.
In the sections that follow, the Register File (RF) and the Peripheral File (PF) are described along
with three important registers in the CPU : the Stack Pointer (SP), the Status Register (ST), and the
Program Counter (PC)
Memory Address
> 0000
> 00FF
> 0132
> 013F
> 01BF
> C005
> FFFF
Register File (RF)
Peripheral File (PF)
Reserved
128 byte PRF
Not Available
16K bytes ROM
> 0100
; 256 byte RAM
> 0133
> 0140
> 01C0
> C006
; 128 byte RAM
Table 4-1. DMC73C168 Memory Map
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DAEWOO ELECTRONICS CO., LTD.
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet DMC73C168.PDF ] | |
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