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PDF HCPL-0931 Data sheet ( Hoja de datos )

Número de pieza HCPL-0931
Descripción (HCPL-09xx) High Speed Digital Isolators
Fabricantes Hewlett-Packard 
Logotipo Hewlett-Packard Logotipo



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No Preview Available ! HCPL-0931 Hoja de datos, Descripción, Manual

Agilent HCPL-9000/-0900, -9030/-0930,
HCPL-9031/-0931, -900J/-090J,
HCPL-901J/-091J, -902J/-092J
High Speed Digital Isolators
Data Sheet
Description
The HCPL-90xx and HCPL-09xx
CMOS digital isolators feature
high speed performance and
excellent transient immunity
specifications. The symmetric
magnetic coupling barrier gives
these devices a typical pulse
width distortion of 2 ns, a typical
propagation delay skew of 4 ns
and 100 Mbaud data rate, making
them the industrys fastest
digital isolators.
The single channel digital isola-
tors (HCPL-9000/-0900) features
an active-low logic output enable.
The dual channel digital isolators
are configured as unidirectional
(HCPL-9030/-0930) and bi-
directional (HCPL-9031/-0931),
operating in full duplex mode
making it ideal for digital
fieldbus applications.
The quad channel digital isola-
tors are configured as unidirec-
tional (HCPL-900J/-090J), two
channels in one direction and
two channels in opposite direc-
tion (HCPL-901J/-091J), and one
channel in one direction and
three channels in opposite
direction (HCPL-902J/-092J).
These high channel density make
them ideally suited to isolating
data conversion devices, parallel
buses and peripheral interfaces.
They are available in 8-pin PDIP,
8-pin Gull Wing, 8-pin SOIC
packages, and 16pin SOIC
narrow-body and wide-body
packages. They are specified over
the temperature range of -40° C
to +100° C.
CAUTION: It is advised that
normal static precautions be
taken in handling and assembly
of this component to prevent
damage and/or degradation,
which may be induced by ESD.
Features
• +3.3V and +5V TTL/CMOS
compatible
• 3 ns max. pulse width distortion
• 6 ns max. propagation delay skew
• 15 ns max. propagation delay
• High speed: 100 MBd
• 15 kV/µs min. common mode
rejection
• Tri-state output
(HCPL-9000/-0900)
• 2500 V RMS isolation
• UL1577 and IEC 61010-1 approved
Applications
• Digital fieldbus isolation
• Multiplexed data transmission
• Computer peripheral interface
• High speed digital systems
• Isolated data interfaces
• Logic level shifting

1 page




HCPL-0931 pdf
HCPL-0900, HCPL-0930 and HCPL-0931 Small Outline SO-8 Package
0.189 (4.80)
0.197 (5.00)
8765
0.228 (5.80)
0.244 (6.20)
0.150 (3.80)
0.157 (4.00)
1234
0.013 (0.33)
0.020 (0.51)
0.054 (1.37)
0.069 (1.75)
0.040 (1.016)
0.060 (1.524)
0.004 (0.10)
0.010 (0.25)
DIMENSIONS: INCHES (MILLIMETERS) MIN
MAX
0.010 (0.25)
0.020 (0.50)
x 45°
0.008 (0.19)
0.010 (0.25)
0.016 (0.40)
0.050 (1.27)
0°
8°
HCPL-900J, HCPL-901J and HCPL-902J Wide Body SOIC-16 Package
0.397 (10.084)
0.413 (10.490)
81
Pin 1 indent
0.394 (10.007)
0.419 (10.643)
0.291 (7.391)
0.299 (7.595)
0.013 (0.330)
0.020 (0.508)
7° TYP
0.080 (2.032)
0.100 (2.54)
0.040 (1.016)
0.060 (1.524)
0.092 (2.337)
0.104 (2.642)
7° TYP
0.004 (0.1016)
0.011 (0.279)
0.009 (0.229)
0.012 (0.305)
DIMENSIONS: INCHES (MILLIMETERS) MIN
MAX
0.287 (7.290)
0.297 (7.544)
0.010
0.020
(0.254)
(0.508)
x
45°
0° 8° TYP
0.016 (0.40)
0.050 (1.27)
5

5 Page





HCPL-0931 arduino
Propagation Delay, Pulse Width
Distortion and Propagation Delay Skew
Propagation Delay is a figure of
merit, which describes how
quickly a logic signal propagates
through a system as illustrated in
Figure 3.
The propagation delay from low to
high, tPLH, is the amount of time
required for an input signal to
propagate to the output, causing
the output to change from low to
high. Similarly, the propagation
delay from high to low, tPHL, is the
amount of time required for the
input signal to propagate to the
output, causing the output to
change from high to low.
Pulse Width Distortion, PWD, is
the difference between tPHL and
tPLH and often determines the
maximum data rate capability of
a transmission system. PWD can
be expressed in percent by
dividing the PWD (in ns) by the
minimum pulse width (in ns)
being transmitted. Typically, PWD
on the order of 20 30% of the
minimum pulse width is tolerable.
Propagation Delay Skew, tPSK,
and Channel-to-Channel Skew,
tCSK, are critical parameters to
consider in parallel data trans-
mission applications where
synchronization of signals on
parallel data lines is a concern.
INPUT
VIN
OUTPUT
VOUT
tPLH
90%
10%
50%
tPHL
90%
10%
Figure 3. Timing Diagrams to Illustrate Propagation Delay, t and t .
PLH PHL
5 V CMOS
0V
VOH
2.5 V CMOS
VOL
VIN
VOUT
VIN
VOUT
50%
2.5 V
CMOS
tPSK
50%
DATA
INPUTS
CLOCK
2.5 V
CMOS
DATA
OUTPUTS
CLOCK
tPSK
tPSK
Figure 5. Parallel Data Transmission.
Figure 4. Timing Diagrams to Illustrate
Propagation Delay Skew.
If the parallel data is being sent
through channels of the digital
isolators, differences in propaga-
tion delays will cause the data to
arrive at the outputs of the
digital isolators at different
times. If this difference in
propagation delay is large
enough, it will limit the maxi-
mum transmission rate at which
parallel data can be sent through
the digital isolators.
tPSK is defined as the difference
between the minimum and
maximum propagation delays,
either tPLH or tPHL, among two or
more devices which are operating
under the same conditions (i.e.,
the same drive current, supply
voltage, output load, and operat-
ing temperature). tCSK is defined
as the difference between the
minimum and maximum propaga-
tion delays, either tPLH or tPHL,
among two or more channels
within a single device (applicable
to dual and quad channel de-
vices) which are operating under
the same conditions.
As illustrated in Figure 4, if the
inputs of two or more devices are
switched either ON or OFF at the
same time, tPSK is the difference
between the minimum propaga-
tion delay, either tPLH or tPHL, and
the maximum propagation delay,
either tPLH or tPHL.
As mentioned earlier, tPSK, can
determine the maximum parallel
data transmission rate. Figure 5
shows the timing diagram of a
typical parallel data transmission
application with both the clock
and data lines being sent through
the digital isolators. The figure
shows data and clock signals at
the inputs and outputs of the
digital isolators. In this case, the
data is clocked off the rising edge
of the clock.
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