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PDF HCPL-0872 Data sheet ( Hoja de datos )

Número de pieza HCPL-0872
Descripción Digital Interface IC
Fabricantes Agilent Technologies 
Logotipo Agilent Technologies Logotipo



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Agilent HCPL-0872
Digital Interface IC
Data Sheet
Features
Interface between HCPL-7860/
786J/7560 and MCU/DSP
Description
The Digital Interface IC, HCPL-
0872 converts the single-bit
data stream from the Isolated
Modulator (such as HCPL-
7860/786J/7560) into fifteen-
bit output words and provides
a serial output interface that is
compatible with SPI®, QSPI®,
and Microwire® protocols,
allowing direct connection to a
microcontroller. The Digital
Interface IC, HCPL-0872 is
available a 300-mil wide SO-16
surface-mount package.
Features of the Digital
Interface IC include five
different conversion modes,
three different pre-trigger
modes, offset calibration, fast
over-range detection, and
adjustable threshold detection.
Programmable features are
configured via the Serial
Configuration port. A second
multiplexed input is available
to allow measurements with a
second isolated modulator
without additional hardware.
5 Conversion Modes for
Resolution/Speed Trade-Off
3 Pre-Trigger Modes
Offset Calibration
Fast 3 µs Over-Range Detection
Adjustable Threshold Detection
Serial I/O (SPI®, QSPI® and
Microwire Compatible)
Offset Calibration
-40°C to +85°C Operating
Temperature Range
Applications
Motor Phase and Rail Current
Sensing
Data Acquisition Systems
Input
Current
VDD1
VDD2
VIN+ MCLK
VIN- MDAT
GND1 GND2
HCPL-7860
1 CCLK
VDD 16
CONFIG
2 CLAT INTER-
CHAN 15
FACE CON
3 CDAT
VINETRESRIO- NSCLK 14
4 MCLK1
FACE
SDAT 13
CH1
5 MDAT1
CS 12
Industrial Process Control
Inverter Current Sensing
MCU General Purpose Current Sensing
or and Monitoring
DSP
HCPL-786J
HCPL-7560
VDD1
VDD2
6 MCLK2
THR1 11
THRES
7
MDAT2 CH2
HOLD OVR1
DETECT
10
Input
VIN+ MCLK
8 GND
& RESET
RESET 9
mCurrent
VIN- MDAT
GND1 GND2
HCPL-0872
u.coA 0.1 µF bypass capacitor must be connected between pins VDD and Ground
et4CAUTION: It is advised that normal static precautions be taken in handling and assembly
eof this component to prevent damage and/or degradation, which may be induced by ESD.
tashSPI and QSPI are trademarks of Motorola Corp.
www.daMicrowire is a trademark of National Semiconductor Inc.

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HCPL-0872 pdf
Absolute Maximum Ratings
Parameter
Symbol Min.
Max.
Units
Storage Temperature
Operating Temperature
Supply Voltage
Input Voltage
Output Voltage
Lead Solder Temperature
TS -55 125 °C
TA -40 85 °C
VDD 0
5.5 V
All Inputs -0.5
VDD + 0.5 V
All Outputs -0.5
VDD + 0.5 V
260°C for 10 sec., 1.6 mm below seating plane
Solder Reflow Temperature Profile
See Reflow Thermal Profile
Notes 1. Agilent Technologies recommends the use of non-chlorinated solder fluxes.
Note
1
Recommended Operating Conditions
Parameter
Ambient Operating Temperature
Supply Voltage
Input Voltage
Electrical Specifications (DC)
Symbol
TA
VDD
All Inputs
Min.
-40
4.5
0
Max.
85
5.5
VDD
Units
°C
V
V
Unless otherwise noted, all Typical specifications are at TA = 25°C and VDD = 5 V, and all Minimum and Maximum
specifications apply over the following ranges: TA = -40°C to +85°C and VDD = 4.5 to 5.5 V.
Parameter
Symbol Min. Typ.
Max. Units Test Conditions Fig.
Supply Current
DC Input Current
Input Logic Low Voltage
Input Logic High Voltage
Output Logic Low Voltage
Output Logic High Voltage
Clock Frequency
(CCLK, MCLK and SCLK)
IDD 3 5 mA fCLK = 10 MHz
IIN
0.001 10
µA
VIL 0.8 V
VIH 3.6
V
VOL
0.15 0.4 V
IOUT = 4 mA
VOH 4.3 5.0
V IOUT = -400 µA
fCLK 20 MHz
Clock Period (CCLK, MCLK and SCLK)
Clock High Level Pulse Width
(CCLK, MCLK and SCLK)
tPER
tPWH
50
20
ns 2, 3
ns 2, 3
Clock Low Level Pulse Width
(CCLK, MCLK and SCLK)
tPWL 20
ns 2, 3
Setup Time from DAT to Rising Edge tSUCLK
of CLK (CDAT, CCLK, MDAT and MCLK)
10
ns 2
DAT Hold Time after Rising Edge
tHDCLK
of CLK (CDAT, CCLK, MDAT and MCLK)
10
ns 2
Setup Time from Falling Edge
of CLAT to First Rising Edge of CCLK
tSUCL1
20
ns 2
Setup Time from Last Rising
Edge of CCLK to Rising Edge of CLAT
tSUCL2
20
ns 2
Delay Time from Falling
Edge of SCLK to SDAT
tDSDAT
15 ns
3
Setup Time from Data
Ready to First Falling Edge of SCLK
tSUS
200
ns 3
Setup Time from CHAN
to falling edge of CS
tSUCHS
20
ns
Reset High Level Pulse Width
tPWR 100
ns
Notes:
1. Agilent recommends the use of non-chlorinated solder fluxes.
5

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HCPL-0872 arduino
Table 3. Pre-Trigger Mode Configuration.
Table 4. Offset Calibration Configuration.
Pre-Trigger Mode
0
1
2
Configuration Data Bits
Bit 7 Bit 6
Low Low
Low High
High Don't Care
Offset Calibration Mode
Off
On
Configuration Data Bits
Bit 3
Low
High
Notes: Bold italic type indicates Default values.
Notes: Bold italic type indicates Default values.
Offset Calibration
Over-Range Detection
The offset calibration circuit
can be used to separately
calibrate the offsets of both
channels 1 and 2. The offset
calibration circuit contains a
separate offset register for
each channel. After an offset
calibration sequence, the offset
registers will contain a value
equal to the measured offset,
which will then be subtracted
from all subsequent
conversions. A hardware reset
(bringing the RESET pin high
for at least 100 ns) is required
to reset the offset calibration
registers to zero.
The following sequence is
recommended for performing
an offset calibration:
1. Select the appropriate
channel using the CHAN pin
(low = channel 1, high =
channel 2).
2. Force zero volts at the input
of the selected isolated
modulator.
3. Send a configuration data
byte to the appropriate
register for the selected
channel (register 0 for
channel 1, register 1 for
channel 2). Bit 3 of the
configuration byte should be
set high to enable offset
calibration mode and bits 4
through 7 should be set to
select conversion mode 1 to
achieve the highest
resolution measurement of
the offset.
4. Perform one complete
conversion cycle by bringing
CS low until SDAT goes
high, indicating completion
of the conversion cycle.
Because bit 3 of the
configuration has been set
high, the uncalibrated
output data from the
conversion will be stored in
the appropriate offset
calibration register and will
be subtracted from all
subsequent conversions on
that channel. If multiple
conversion cycles are
performed while the offset
calibration mode is enabled,
the uncalibrated data from
the last conversion cycle
will be stored in the offset
calibration register.
5. Send another configuration
byte to the appropriate
register for the selected
channel, setting bit 3 low to
disable calibration mode and
setting bits 4 through 7 to
select the desired conversion
mode for subsequent
conversions on that channel.
To calibrate both channels,
perform the above sequence
for each channel. The offset
calibration sequence can be
performed as often as needed.
Table 4 below summarizes how
to turn the offset calibration
mode on or off using bit 3 of
configuration registers 0 and 1.
The over-range detection
circuit allows fast detection of
when the magnitude of the
input signal on channel 1 is
near or beyond full-scale,
causing the OVR1 output to go
high. This circuit can be very
useful in current-sensing
applications for quickly
detecting when a short-circuit
occurs. The over-range
detection circuit works by
detecting when the modulator
output data has not changed
state for at least 25 clock
cycles in a row, indicating that
the input signal is near or
beyond full-scale, positive or
negative. Typical response time
to over-range signals is less
than 3µs.
The over-range circuit actually
begins to indicate an over-
range condition when the
magnitude of the input signal
exceeds approximately 250 mV;
it starts to generate periodic
short pulses on OVR1, which
get longer and more frequent
as the input signal approaches
full scale. The OVR1 output
stays high continuously when
the input is beyond full-scale.
The over-range detection
circuit continuously monitors
channel 1 independent of
which channel is selected with
the CHAN signal. This allows
continuous monitoring of
channel 1 for faults while
converting an input signal on
channel 2.
11

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