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PDF DM8556 Data sheet ( Hoja de datos )
| Número de pieza | DM8556 | |
| Descripción | TRI-STATE Programmable Binary Counters | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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August 1989
DM7556 DM8556 TRI-STATE Programmable
Binary Counters
General Description
These circuits are synchronous edge-sensitive fully-pro-
grammable 4-bit counters The counters feature both con-
ventional totem-pole and TRI-STATE outputs such that
when the outputs are in the high impedance mode they can
be used to enter data from the bus lines In addition the
clear input operates completely independent of all other in-
puts During the programming operation data is loaded into
the flip-flops on the positive-going edge of the clock pulse
To facilitate cascading of these counters the MAX COUNT
output can be tied directly into the count enable input of the
next counter
Features
Y Typical clock frequency 35 MHz
Y TRI-STATE outputs
Y Fully independent clear
Y Synchronous loading
Y Cascading circuitry provided internally
Connection Diagram
Dual-In-Line Package
Function Table
Order Number DM7556J or DM8556N
See NS Package Number J16A or N16A
TL F 6588 – 1
Control Inputs
I O Ports
Active Outputs
LOAD CE CLK OD Reset I OA I OB I OC I OD QA QB QC QD
H XX L H
L L L L L L LL
H XXH H
Z Z Z Z L L LL
H X L L L QA0 QB0 QC0 QD0 QA0 QB0 QC0 QD0
H XLH L
Z Z Z Z QA0 QB0 QC0 QD0
L Hu L L
ab
c d A B CD
H LuL L
COUNT
COUNT
H LuH L
ZZZZ
COUNT
The I O pins are used as inputs when they are TRI-STATED and the LOAD input is Low They are outputs and active
when LOAD input is High and OD is Low
H e High Level (Steady State)
L e Low Level (Steady State)
X e Don’t Care including transitions
a b c d e The level of the steady state input at inputs A B C D respectively
QA0 QB0 QC0 QD0 e The level of QA QB QC QD respectively before the indicated steady state input conditions
were established
TRI-STATE is a registered trademark of the National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 6588
RRD-B30M105 Printed in U S A
1 page  
Timing Diagram
75 8556 Typical Clear Preset Count Inhibit Sequence
Sequence
(1) Clear to zero
(2) Load binary five
(3) Count six seven eight nine ten eleven twelve thirteen fourteen fifteen zero
(4) Disable TRI-STATE outputs
(5) Disable counter
(6) Count to one
TL F 6588 – 3
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet DM8556.PDF ] | |
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