|
|
PDF TEA5880TS Data sheet ( Hoja de datos )
| Número de pieza | TEA5880TS | |
| Descripción | Integrated FM Stereo Radio ic For Host Processor Tuning in Handheld Applications | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de TEA5880TS (archivo pdf) en la parte inferior de esta página. Total 27 Páginas | ||
|
No Preview Available !
TEA5880TS
Integrated FM stereo radio IC for host processor tuning in
handheld applications
Rev. 02 — 26 April 2004
Preliminary data sheet
1. General description
The TEA5880TS stereo FM radio IC dramatically reduces the printed-circuit board area
(only 100 mm2) needed to integrate FM radio functionality into portable devices. This
makes it invaluable for any application where space is at a premium.
Relying on a system host processor for radio tuning, the TEA5880TS is ideally suited for
powerful devices such as PDAs, notebooks, portable CD and MP3 players.
2. Features
s No alignments necessary
s Complete adjustment-free stereo decoder; no external crystal required
s Fully integrated MPX VCO circuit
s Fully integrated low IF selectivity and demodulation
s The full integration level means no or few external components required
s No external FM discriminator needed due to full integration
s Built-in adjacent channel interference total reduction (no 114 kHz, no 190 kHz)
s The level of the incoming signal at which the radio must lock is software programmable
s Due to new tuning concept, the tuning is independent of the channel spacing
s Very high sensitivity due to integrated low noise RF input amplifier
s RF Automatic Gain Control (AGC) circuit
s Standby mode for power-down, no power switch circuitry required
s 2.7 V minimum supply voltage
s MPX output for RDS
s 3-wire bus
s In combination with the host, fast, low power operation of preset mode, manual search,
automatic search and automatic store are possible
s Host can be in Sleep mode after tuning; a minute retuning is recommended to
compensate for temperature and voltage fluctuations
s Covers all Japanese, European and US bands.
1 page  
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx
xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x
RFIN
RFGND
LR1
17
VCC1
18
VCC1
19
LL1
20
reserved
21
MICROCONTROLLER
R/W
6
CLOCK
8
DATA
7
QUADRATURE
OSCILLATOR
TUNING
SYSTEM
QUADRATURE
MIXER
SELECTIVITY
DEMODULATOR
DIGITAL
INTERFACE
STEREO
DECODER
DE-EMPHASIS
50/75 µs
LEVEL VOLTAGE
GENERATOR
DE-EMPHASIS
15 kHz
10
MIXER 11
AUDL
AUDR
STABILISATOR
POWER
SWITCH
5 4 3, 13, 24
VCCA VCCD GND
TEA5880TS
9 MPX
12
LED
14, 15, 16, 22, 23
001aaa666
n.c.
Fig 2. Block diagram (no external components).
5 Page 
Philips Semiconductors
TEA5880TS
Integrated FM stereo radio IC for host processor tuning
Table 12: CTRL_B - (address 4h) bit description
Bit Symbol
Description
14 to 11 -
address bits
10 L_CNT
latch counter: a transition from logic 1 to logic 0 will latch the
COUNTER register into the PISO (reading the PISO hereafter will read
the COUNTER register)
9 L_STS
latch status: a transition from logic 1 to logic 0 will latch the STATUS
register into the PISO (reading the PISO hereafter will read the STATUS
register)
8 to 6 -
reserved for output level control; should be written with 4 (100b);
see Table 13
5
DEEMP
de-emphasis: logic 1 is 75 µs (USA), logic 0 is 50 µs (Europe, Japan)
4 PISO_CLR a transition from logic 1 to logic 0 will clear the PISO; the PISO should
be clear before reading the STATUS/COUNTER register
3
CNT_RST
a transition from logic 1 to logic 0 will clear both counter 1 and counter 2
2
CNT1_EN
counter 1 enabled (counting mode) when set to logic 1
1-
should be written to logic 0
0 MONO
mono mode when set to logic 1, stereo mode when set to logic 0
Table 13: Description of output level control register bits
Value
Decimal
0000b
0
0001b
1
0010b
2
0011b
3
0100b
4
0101b
5
0110b
6
Output level
12 mV
20 mV
35 mV
60 mV
100 mV
170 mV
200 mV
Table 14: CAP_FM - (address 5h) bit description [1]
Bit Symbol
Description
14 to 11 -
address bits
10 -
reserved for capacitor extra current; this bit should be written to logic 1
by any access to the CAP_FM to ensure that the device functions
properly
9 to 8 -
reserved, should be written to logic 0
7 to 0 FC[7:0]
FM capacitor bank switches for adjusting the FM (RF) frequency in big
steps. Every bit, when set, will switch on a capacitor with a weight
according to its position i.e. bit 0 has weight 1, bit 1 has weight 2, bit 2
has weight 4 etc, bit 6 has weight 64, except for bit 7, which also has the
same weight as bit 6; there is thus only 71⁄2 effective bits; this means
that the value range 0 to 127 will switch on different capacitors the value
range 128 to 191 switches on the same capacitors as range 64 to 127,
the value range 192 to 255 will switch on different capacitors (an
overlapped range of 64 values caused when FC[7:6] = 01b or 10b)
[1] The frequency is decreased when increasing the content of this register (more capacitors).
9397 750 13022
Preliminary data sheet
Rev. 02 — 26 April 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
11 of 27
11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet TEA5880TS.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| TEA5880TS | Integrated FM Stereo Radio ic For Host Processor Tuning in Handheld Applications | NXP Semiconductors |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |