|
|
PDF IBM25PPC405GP Data sheet ( Hoja de datos )
| Número de pieza | IBM25PPC405GP | |
| Descripción | Embedded Controller | |
| Fabricantes | IBM Microelectronics | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de IBM25PPC405GP (archivo pdf) en la parte inferior de esta página. Total 60 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
PowerPC 405GP Embedded Processor Data Sheet
Features
• IBM PowerPC 405 32-bit RISC processor core
operating up to 266MHz
• Synchronous DRAM (SDRAM) interface
operating up to 133MHz
- 32-bit interface for non-ECC applications
- 40-bit interface serves 32 bits of data plus 8
check bits for ECC applications
• PCI Revision 2.2 compliant interface (32-bit, up
to 66MHz)
- Synchronous or asynchronous PCI Bus
interface
- Internal or external PCI Bus Arbiter
• Ethernet 10/100Mbps (full-duplex) support with
media independent interface (MII)
• 4KB on-chip memory (OCM)
• External peripheral bus
• Programmable interrupt controller supports
seven external and 19 internal edge triggered or
level-sensitive interrupts
- Flash ROM/Boot ROM interface
- Direct support for 8-, 16-, or 32-bit SRAM
and external peripherals
- Up to eight devices
- External Mastering supported
• Programmable timers
• Two serial ports (16550 compatible UART)
• One IIC interface
• General purpose I/O (GPIO) available
• DMA support for external peripherals, internal
• Supports JTAG for board level testing
UART and memory
DataSheet4U.c• omInternal processor local Bus (PLB) runs at
- Scatter-gather chaining supported
SDRAM interface frequency
- Four channels
• Supports PowerPC processor boot from PCI
memory
DataShee
Description
Designed specifically to address embedded
applications, the PowerPC 405GP (PPC405GP)
provides a high-performance, low-power solution
that interfaces to a wide range of peripherals by
incorporating on-chip power management features
and lower power dissipation requirements.
This chip contains a high-performance RISC
processor core, SDRAM controller, PCI bus
interface, Ethernet interface, control for external
ROM and peripherals, DMA with scatter-gather
support, serial ports, IIC interface, and general
purpose I/O.
Technology: IBM CMOS SA-12E, 0.25 µm
(0.18 µm Leff)
Package: 456-ball (35mm or 27mm), or 413-ball
(25mm) enhanced plastic ball grid array (E-PBGA)
Power (typical): TBDW at 133MHz, 1.5W at
200MHz, 2W at 266MHz
DataSheet4U.com
6/20/03
DataSheet4 U .com
Page 1 of 60
1 page  
www.DataSheet4U.com
et4U.com
PowerPC 405GP Embedded Processor Data Sheet
PPC405GP Embedded Controller Functional Block Diagram
Universal
Interrupt
Controller
8KB
D-Cache
Clock
Control
Reset
Power
Mgmt
Timers
MMU
DOCM
IOCM
PPC405
Processor Core
JTAG
DCU
Trace
ICU
OCM
SRAM
OCM
Control
DCR Bus
DCRs
GPIO IIC UART UART
16KB Arb
I-Cache
On-chip Peripheral Bus (OPB)
DMA
Controller
(4-Channel)
OPB
Bridge
MAL
Ethernet
Arb Processor Local Bus (PLB)
Code
Decompression
(CodePack)
DataSheet4U.com
SDRAM
Controller
External
Bus
Controller
External
Bus Master
Controller
PCI Bridge
13-bit addr
32-bit data
32-bit addr
32-bit data
66 MHz max (async)
33 MHz max (sync)
MII
DataShee
The PPC405GP is designed using the IBM Microelectronics Blue LogicTM methodology in which major
functional blocks are integrated together to create an application-specific ASIC product. This approach
provides a consistent way to create complex ASICs using IBM CoreConnectTM Bus Architecture.
DataSheet4U.com
6/20/03
DataSheet4 U .com
Page 5 of 60
5 Page 
www.DataSheet4U.com
et4U.com
PowerPC 405GP Embedded Processor Data Sheet
Serial Interface
• One 8-pin UART and one 4-pin UART interface provided
• Selectable internal or external serial clock to allow a wide range of baud rates
• Register compatibility with NS16550 register set
• Complete status reporting capability
• Transmitter and receiver are each buffered with 16-byte FIFOs when in FIFO mode
• Fully programmable serial-interface characteristics
• Supports DMA using internal DMA engine
IIC Bus Interface
• Compliant with Philips® Semiconductors I2C Specification, dated 1995
• Operation at 100kHz or 400kHz
• 8-bit data
• 10- or 7-bit address
• Slave transmitter and receiver
• Master transmitter and receiver
DataSheet4U.com
• Multiple bus masters
• Supports fixed VDD IIC interface
• Two independent 4 x 1 byte data buffers
• Twelve memory-mapped, fully programmable configuration registers
• One programmable interrupt request signal
• Provides full management of all IIC bus protocol
• Programmable error recovery
DataShee
DataSheet4U.com
6/20/03
DataSheet4 U .com
Page 11 of 60
11 Page | ||
| Páginas | Total 60 Páginas | |
| PDF Descargar | [ Datasheet IBM25PPC405GP.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| IBM25PPC405GP | Embedded Controller | IBM Microelectronics |
| IBM25PPC405GP | Power PC Embedded Processor | IBM Microelectronics |
| IBM25PPC405GPR | Embedded Processor | IBM Microelectronics |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |