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PDF 29LV160BE Data sheet ( Hoja de datos )

Número de pieza 29LV160BE
Descripción MBM29LV160BE
Fabricantes Fujitsu Media Devices 
Logotipo Fujitsu Media Devices Logotipo



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No Preview Available ! 29LV160BE Hoja de datos, Descripción, Manual

FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-20883-2E
FLASH MEMORY
CMOS
16M (2M × 8/1M × 16) BIT
MBM29LV160TE/BE -www.DataSheet4U.com
70/90/12
s GENERAL DESCRIPTION
The MBM29LV160TE/BE is a 16M-bit, 3.0 V-only Flash memory organized as 2M bytes of 8 bits each or 1M words
of 16 bits each. The MBM29LV160TE/BE is offered in a 48-pin TSOP (I), 48-pin CSOP and 48-ball FBGA
packages. The device is designed to be programmed in-system with the standard system 3.0 V VCC supply. 12.0
V VPP and 5.0 V VCC are not required for write or erase operations. The device can also be reprogrammed in
standard EPROM programmers.
The standard MBM29LV160TE/BE offers access times of 70 ns, 90 ns and 120 ns, allowing operation of high-
speed microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE),
write enable (WE), and output enable (OE) controls.
The MBM29LV160TE/BE is pin and command set compatible with JEDEC standard E2PROMs. Commands are
written to the command register using standard microprocessor write timings. Register contents serve as input
to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch
addresses and data needed for the programming and erase operations. Reading data out of the device is similar
to reading from 5.0 V and 12.0 V Flash or EPROM devices.
The MBM29LV160TE/BE is programmed by executing the program command sequence. This will invoke the
Embedded ProgramTM* Algorithm which is an internal algorithm that automatically times the program pulse widths
and verifies proper cell margins. Typically, each sector can be programmed and verified in about 0.5 seconds.
Erase is accomplished by executing the erase command sequence. This will invoke the Embedded EraseTM*
Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed
before executing the erase operation. During erase, the device automatically times the erase pulse widths and
verifies proper cell margins.
Any individual sector is typically erased and verified in 1.0 second. (If already preprogrammed.)
within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word
at a time using the EPROM programming mechanism of hot electron injection.
s PRODUCT LINE UP
(Continued)
Part No.
Ordering Part No.
VCC
=
3.3
V
+0.3 V
–0.3 V
VCC
=
3.0
V
+0.6 V
–0.3 V
Max. Address Access Time (ns)
Max. CE Access Time (ns)
Max. OE Access Time (ns)
MBM29LV160TE/160BE
70 —
— 90 12
70 90 120
70 90 120
30 35 50

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29LV160BE pdf
MBM29LV160TE/BE-70/90/12
(Continued)
www.DataSheet4U.com
A1 A3
B1 A4
C1 A2
D1 A1
E1 A0
F1 CE
G1 OE
H1 VSS
A1
A2
A3
A4
A5
A6
A7
A17
A18
RY/BY
N.C.
N.C.
RESET
WE
N.C.
A19
A8
A9
A10
A11
A12
A13
A14
A15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
CSOP
(TOP VIEW)
(Marking side)
48 A0
47 CE
46 VSS
45 OE
44 DQ0
43 DQ8
42 DQ1
41 DQ9
40 DQ2
39 DQ10
38 DQ3
37 DQ11
36 VCC
35 DQ4
34 DQ12
33 DQ5
32 DQ13
31 DQ6
30 DQ14
29 DQ7
28 DQ15/A-1
27 VSS
26 BYTE
25 A16
(LCC-48P-M03)
FBGA
(TOP VIEW)
Marking side
A1 A2 A3 A4 A5 A6
B1 B2 B3 B4 B5 B6
C1 C2 C3 C4 C5 C6
D1 D2 D3 D4 D5 D6
E1 E2 E3 E4 E5 E6
F1 F2 F3 F4 F5 F6
G1 G2 G3 G4 G5 G6
H1 H2 H3 H4 H5 H6
(BGA-48P-M11)
A2 A7 A3 RY/BY A4 WE A5 A9 A6 A13
B2 A17 B3 N.C. B4 RESET B5 A8 B6 A12
C2 A6 C3 A18 C4 N.C. C5 A10 C6 A14
D2 A5 D3 N.C. D4 A19 D5 A11 D6 A15
E2 DQ0 E3 DQ2 E4 DQ5 E5 DQ7 E6
A16
F2 DQ8 F3 DQ10 F4 DQ12 F5 DQ14 F6 BYTE
G2 DQ9 G3 DQ11 G4 VCC G5 DQ13 G6 DQ15/A-1
H2 DQ1 H3 DQ3 H4 DQ4 H5 DQ6 H6 VSS
5

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29LV160BE arduino
MBM29LV160TE/BE-70/90/12
s FUNCTIONAL DESCRIPTION
• Read Mode
The MBM29LV160TE/BE has two control functions which must be satisfied in order to obtain data at the outputs.
CE is the power control and should be used for a device selection. OE is the output control and should be used
to gate data to the output pins if a device is selected.
Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable
access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output
enable access time is the delay from the falling edge of OE to valid data at the output pins. (Assuming the
addresses have been stable for at least tACC - tOE time.) When reading out a data without changing addresses
after power-up, it is necessary to input hardware reset or to change CE pin from “H” or “L”.
www.DataSheet4U.com
• Standby Mode
There are two ways to implement the standby mode on the MBM29LV160TE/BE devices. One is by using both
the CE and RESET pins; the other via the RESET pin only.
When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at VCC ±0.3 V.
Under this condition the current consumed is less than 5 µA max. During Embedded Algorithm operation, VCC
Active current (ICC2) is required even CE = “H”. The device can be read with standard access time (tCE) from
either of these standby modes.
When using the RESET pin only, a CMOS standby mode is achieved with the RESET input held at VSS ±0.3 V
(CE = “H” or “L”). Under this condition the current consumed is less than 5 µA max. Once the RESET pin is
taken high, the device requires tRH of wake up time before outputs are valid for read access.
In the standby mode, the outputs are in the high-impedance state, independent of the OE input.
• Automatic Sleep Mode
There is a function called automatic sleep mode to restrain power consumption during read-out of
MBM29LV160TE/BE data. This mode can be used effectively with an application requesting low power con-
sumption such as handy terminals.
To activate this mode, MBM29LV160TE/BE automatically switches itself to low power mode when addresses
remain stable for 150 ns. It is not necessary to control CE, WE, and OE in this mode. During such mode, the
current consumed is typically 1 µA (CMOS Level).
Standard address access timings provide new data when addresses are changed. While in sleep mode, output
data is latched and always available to the system.
• Output Disable
If the OE input is at a logic high level (VIH), output from the device is disabled. This will cause the output pins to
be in a high-impedance state.
• Autoselect
The Autoselect mode allows the reading out of a binary code from the device and will identify its manufacturer
and type. The intent is to allow programming equipment to automatically match the device to be programmed
with its corresponding programming algorithm. The Autoselect command may also be used to check the status
of write-protected sectors. (See Tables 4.1 and 4.2.) This mode is functional over the entire temperature range
of the device.
To activate this mode, the programming equipment must force VID (11.5 V to 12.5 V) on address pin A9. Two
identifier bytes may then be sequenced from the devices outputs by toggling address A0 from VIL to VIH. All
addresses are DON’T CARES except A0, A1, and A6 (A-1). (See Table 2 or Table 3.)
11

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