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PDF EP1C12T Data sheet ( Hoja de datos )

Número de pieza EP1C12T
Descripción Cyclone FPGA Family
Fabricantes Altera 
Logotipo Altera Logotipo



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March 2003, ver. 1.1
®
Cyclone
FPGA Family
Data Sheet
Introduction
Preliminary
Information
Features...
The CycloneTM field programmable gate array family is based on a 1.5-V,
0.13-µm, all-layer copper SRAM process, with densities up to 20,060 logic
elements (LEs) and up to 288 Kbits of RAM. With features like phase-
locked loops (PLLs) for clocking and a dedicated double data rate (DDR)
interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory
requirements, Cyclone devices are a cost-effective solution for data-path
applications. Cyclone devices support various I/O standards, including
LVDS at data rates up to 311 megabits per second (Mbps) and 66-MHz,
32-bit peripheral component interconnect (PCI), for interfacing with and
supporting ASSP and ASIC devices. Altera also offers new low-cost serial
configuration devices to configure Cyclone devices.
2,910 to 20,060 LEs, see Table 1
Up to 294,912 RAM bits (36,864 bytes)
Supports configuration through low-cost serial configuration device
Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards
Support for 66-MHz, 32-bit PCI standard
Low speed (311 Mbps) LVDS I/O support
Up to two PLLs per device provide clock multiplication and phase
shifting
Up to eight global clock lines with six clock resources available per
logic array block (LAB) row
Support for external memory, including DDR SDRAM (133 MHz),
FCRAM, and single data rate (SDR) SDRAM
Support for multiple intellectual property (IP) cores, including
AlteraMegaCorefunctions and Altera Megafunctions Partners
Program (AMPPSM) megafunctions
Table 1. Cyclone Device Features
Feature
EP1C3
LEs
M4K RAM blocks (128 × 36 bits)
Total RAM bits
PLLs
Maximum user I/O pins (1)
2,910
13
59,904
1
104
Note to Table 1:
(1) This parameter includes global clock pins.
EP1C4
4,000
17
78,336
2
301
EP1C6
5,980
20
92,160
2
185
EP1C12
12,060
52
239,616
2
249
EP1C20
20,060
64
294,912
2
301
Altera Corporation
DS-CYCLONE-1.1
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EP1C12T pdf
Preliminary Information
Figure 1. Cyclone EP1C12 Device Block Diagram
IOEs
Cyclone FPGA Family Data Sheet
Logic Array
PLL
EP1C12 Device
M4K Blocks
The number of M4K RAM blocks, PLLs, rows, and columns vary per
device. Table 4 lists the resources available in each Cyclone device.
Table 4. Cyclone Device Resources
Device
EP1C3
EP1C4
EP1C6
EP1C12
EP1C20
M4K RAM
Columns
Blocks
1 13
1 17
1 20
2 52
2 64
PLLs LAB Columns LAB Rows
1 24 13
2 26 17
2 32 20
2 48 26
2 64 32
Altera Corporation
5

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EP1C12T arduino
Preliminary Information
Cyclone FPGA Family Data Sheet
addnsub Signal
The LE’s dynamic adder/subtractor feature saves logic resources by using
one set of LEs to implement both an adder and a subtractor. This feature
is controlled by the LAB-wide control signal addnsub. The addnsub
signal sets the LAB to perform either A + B or A B. The LUT computes
addition; subtraction is computed by adding the two’s complement of the
intended subtractor. The LAB-wide signal converts to two’s complement
by inverting the B bits within the LAB and setting carry-in = 1 to add one
to the least significant bit (LSB). The LSB of an adder/subtractor must be
placed in the first LE of the LAB, where the LAB-wide addnsub signal
automatically sets the carry-in to 1. The Quartus II Compiler
automatically places and uses the adder/subtractor feature when using
adder/subtractor parameterized functions.
LE Operating Modes
The Cyclone LE can operate in one of the following modes:
Normal mode
Dynamic arithmetic mode
Each mode uses LE resources differently. In each mode, eight available
inputs to the LEthe four data inputs from the LAB local interconnect,
carry-in0 and carry-in1 from the previous LE, the LAB carry-in
from the previous carry-chain LAB, and the register chain
connectionare directed to different destinations to implement the
desired logic function. LAB-wide signals provide clock, asynchronous
clear, asynchronous preset/load, synchronous clear, synchronous load,
and clock enable control for the register. These LAB-wide signals are
available in all LE modes. The addnsub control signal is allowed in
arithmetic mode.
The Quartus II software, in conjunction with parameterized functions
such as library of parameterized modules (LPM) functions, automatically
chooses the appropriate mode for common functions such as counters,
adders, subtractors, and arithmetic functions. If required, the designer can
also create special-purpose functions that specify which LE operating
mode to use for optimal performance.
Altera Corporation
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