PDF ICS950508 Data sheet ( Hoja de datos )

Número de pieza	ICS950508
Descripción	Programmable Timing Control Hub
Fabricantes	Integrated Circuit Systems
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No Preview Available ! Integrated Circuit Systems, Inc. ICS950508 Programmable Timing Control Hub™ for PII/III™ Recommended Application: 810/810E/815 and 815 B-Step type chipset Output Features: • 2 - CPUs @ 2.5V • 13 - SDRAM @ 3.3V • 3 - 3V66 @ 3.3V • 8 - PCI @3.3V • 1 - 24/48MHz@ 3.3V • 1 - 48MHz @ 3.3V fixed • 1 - REF @3.3V, 14.318MHz Features/Benefits: • Programmable output frequency. • Programmable output divider ratios. • Programmable output rise/fall time. • Programmable output skew. • Programmable spread percentage for EMI control. • Watchdog timer technology to reset system if system malfunctions. • Programmable watch dog safe frequency. • Support I2C Index read/write and block read/write operations. • Uses external 14.318MHz crystal. Key Specifications: Pin Configuration VDDREF X1 X2 GND GND 3V66_0 3V66_1 3V66_2 VDD3V66 VDDPCI 1FS0/PCICLK0 1FS1/PCICLK1 1SEL24_48#/PCICLK2 GND PCICLK3 PCICLK4 PCICLK5 VDDPCI PCICLK6 PCICLK7 GND Vtt_PWRGD/PD# SCLK SDATA VDDSDR SDRAM11 SDRAM10 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 REF0/FS41 55 VDDLAPIC 54 IOAPIC 53 VDDLCPU 52 CPUCLK0 51 CPUCLK1 50 GND 49 GND 48 SDRAM0 47 SDRAM1 46 SDRAM2 45 VDDSDR 44 SDRAM3 43 SDRAM4 42 SDRAM5 41 GND 40 SDRAM6 39 SDRAM7 38 SDRAM_F 37 VDDSDR 36 GND 35 24_48MHz/FS2* 34 48MHZ/FS3* 33 VDD48 32 VDDSDR 31 SDRAM8 30 SDRAM9 29 GND 56-Pin 300-mil SSOP 1. These pins will have 1.5 to 2X drive strength. * Internal Pull-up resistor of 120K to VDD • CPU Output Jitter: <250ps • IOAPIC Output Jitter: <500ps • 48MHz, 3V66, PCI Output Jitter: <500ps Block Diagram • Ref Output Jitter. <1000ps • CPU Output Skew: <175ps • PCI Output Skew: <500ps • 3V66 Output Skew <175ps PLL2 /2 48MHz 24_48MHz • For group skew timing, please refer to the Group Timing Relationship Table. X1 XTAL X2 OSC REF0 PLL1 Spread Spectrum FS(4:0) PD# SEL24_48# Vtt_PWRGD SDATA SCLK Control Logic Config. Reg. CPU DIVDER SDRAM DIVDER IOAPIC DIVDER PCI DIVDER 3V66 DIVDER 2 CPUCLK (1:0) 12 SDRAM (11:0) SDRAM_F IOAPIC PCICLK (7:0) 8 3V66 (2:0) 3 0470E—04/06/05 1 page Integrated Circuit Systems, Inc. Byte 1: Output Control Register (1 = enable, 0 = disable) Bit Pin# PWD Bit 7 - X Readback FS3# Bit 6 - X Readback FS0# Bit 5 - X Readback FS2# Bit 4 35 1 24MHz Bit 3 - 1 (Reserved) Bit 2 34 1 48MHz Bit 1 - 1 (Reserved) Bit 0 38 1 SDRAM_F Byte 2: Output Control Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 39 40 42 43 44 46 47 48 PWD 1 1 1 1 1 1 1 1 SDRAM7 SDRAM6 SDRAM5 SDRAM4 SDRAM3 SDRAM2 SDRAM1 SDRAM0 Byte 3: Output Control Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 20 19 17 16 15 13 12 11 PWD 1 1 1 1 1 1 1 1 PCICLK7 PCICLK6 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0 Description Description Description Byte 4: Output Control Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 8 6 7 - 54 - 51 52 PWD 1 1 1 X 1 X 1 1 3V66_2 3V66_0 3V66_1 Readback FS4# IOAPIC Readback FS1# CPUCLK1 CPUCLK0 Description 0470E—04/06/05 5 ICS950508 5 Page Integrated Circuit Systems, Inc. ICS950508 Absolute Maximum Ratings Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . 4.6 V I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . 3.6V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Group Timing Relationship Table1 Group CPU 66MHz CPU 100MHz CPU 133MHz CPU 133MHz SDRAM 100MHz SDRAM 100MHz SDRAM 100MHz SDRAM 133MHz Offset Tolerance Offset Tolerance Offset Tolerance Offset Tolerance CPU to SDRAM 2.5ns 500ps 5.0ns 500ps 0.0ns 500ps 3.75ns 500ps CPU to 3V66 7.5ns 500ps 5.0ns 500ps 0.0ns 500ps 0.0ns 500ps SDRAM to 3V66 0.0ns 500ps 0.0ns 500ps 0.0ns 500ps 3.75ns 500ps 3V66 to PCI 1.5-3.5ns 500ps 1.5-3.5ns 500ps 1.5-3.5ns 500ps 1.5 - 3.5ns 500ps PCI to PCI 0.0ns 1.0ns 0.0ns 1.0ns 0.0ns 1.0ns 0.0ns 1.0ns USB & DOT Asynch N/A Asynch N/A Asynch N/A Asynch N/A Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +5%, VDDL=2.5 V+ 5%(unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current VIH VIL IIH IIL1 IIL2 IDD3.3OP VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors CL = 0 pF; Select @ 66M 2 VSS - 0.3 -5 -5 -200 VDD + 0.3 0.8 5 100 V V mA mA mA mA Power Down Supply Current IDD3.3PD CL = 0 pF; With input address to Vdd or GND 600 mA Input frequency Fi VDD = 3.3 V; Pin Inductance Input Capacitance1 Lpin CIN Logic Inputs Cout Out put pin capacitance Transition Time1 Settling Time1 Clk Stabilization1 CINX Ttrans Ts TSTAB X1 & X2 pins To 1st crossing of target Freq. From 1st crossing to 1% target Freq. From VDD = 3.3 V to 1% target Freq. Delay tPZH,tPZH output enable delay (all outputs) tPLZ,tPZH output disable delay (all outputs) 1Guaranteed by design, not 100% tested in production. 14.318 7 5 6 27 45 3 3 3 1 10 1 10 MHz nH pF pF pF mS mS mS nS nS 0470E—04/06/05 11 11 Page

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