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PDF ICS950703 Data sheet ( Hoja de datos )

Número de pieza ICS950703
Descripción Programmable Timing Control Hub
Fabricantes Integrated Circuit Systems 
Logotipo Integrated Circuit Systems Logotipo



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Integrated
Circuit
Systems, Inc.
ICS950703
ProgrammableTiming Control HubTM for P4TM
Recommended Application:
Intel Tehema and Tehema-E Chipsets
Output Features:
• 4 Differential CPU Clock Pairs @ 3.3V
• 2 - 3V MREF clocks for memory reference seeds,
(separate single ended but 180 degrees out of phase)
• 4 - 66MHz 3V66 output
• 10 - 3V 33MHz PCI clocks
• 2 - 48MHz clocks (180 degrees out of phase)
• 2 - 14.318 reference output (180 degrees out of phase)
Key Specifications:
3V66 Output jitter <300ps
• CPU Output Jitter <200ps
• MREF Output jitter <250ps
Features/Benefits:
• QuadRomTM frequency selection.
• Programmable asynchronous 3V66/PCI frequency.
• Programmable output frequency.
• Programmable output divider ratios.
• Programmable output rise/fall time.
• Programmable output skew.
• Programmable spread percentage for EMI control.
• Programmable watch dog safe frequency.
• Support I2C Index read/write and block read/write
operations.
• Uses external 14.318MHz reference input.
Frequency Table
Bit4 Bit3 Bit2 Bit1 Bit0 CPU MREF
Sel133/100 FS3 FS2 FS1 FS0 MHz MHz
0 0 0 0 0 90.00 45.00
0 0 0 0 1 100.00 50.00
0 0 0 1 0 100.90 50.45
0 0 0 1 1 103.00 51.50
0 0 1 0 0 105.00 52.50
0 0 1 0 1 108.00 54.00
0 0 1 1 0 110.00 55.00
0 0 1 1 1 112.00 56.00
0 1 0 0 0 115.00 57.50
0 1 0 0 1 118.00 59.00
0 1 0 1 0 120.00 60.00
0 1 0 1 1 122.00 61.00
0 1 1 0 0 125.00 62.50
0 1 1 0 1 127.00 63.50
0 1 1 1 0 130.00 65.00
0 1 1 1 1 133.60 66.80
1 0 0 0 0 120.00 60.00
1 0 0 0 1 133.33 66.67
1 0 0 1 0 133.90 66.95
1 0 0 1 1 136.00 68.00
1 0 1 0 0 138.00 69.00
1 0 1 0 1 140.00 70.00
1 0 1 1 0 142.00 71.00
1 0 1 1 1 144.00 72.00
1 1 0 0 0 145.00 72.50
1 1 0 0 1 148.00 74.00
1 1 0 1 0 150.00 75.00
1 1 0 1 1 152.00 76.00
1 1 1 0 0 154.00 77.00
1 1 1 0 1 156.00 78.00
1 1 1 1 0 158.00 79.00
1 1 1 1 1 160.00 80.00
PCI
MHz
30.00
33.33
33.63
34.33
35.00
36.00
36.67
37.33
38.33
39.33
40.00
40.67
41.67
42.33
43.33
44.53
30.00
33.33
33.48
34.00
34.50
35.00
35.50
36.00
36.25
37.00
37.50
38.00
38.50
39.00
39.50
40.00
3V66
MHz
60.00
66.67
67.27
68.67
70.00
72.00
73.33
74.67
76.67
78.67
80.00
81.33
83.33
84.67
86.67
89.07
60.00
66.67
66.95
68.00
69.00
70.00
71.00
72.00
72.50
74.00
75.00
76.00
77.00
78.00
79.00
80.00
Pin Configuration
GND 1
56 VDDMREF
MULTSEL0/REF0 2
55 3VMREF
MULTSEL1/REF1 3
54 3VMREF_B
VDDREF 4
53 GNDMREF
X1 5
52 SCLK
X2 6
51 CPUCLKT3
GNDREF 7
50 CPUCLKC3
PCICLK0 8
PCICLK1 9
49 VDDCPU
48 CPUCLKT2
VDDPCI 10
47 CPUCLKC2
PCICLK2 11
46 GNDCPU
PCICLK3 12
45 CPUCLKT1
GNDPCI 13
44 CPUCLKC1
PCICLK4 14
43 VDDCPU
PCICLK5 15
42 CPUCLKT0
VDDPCI 16
41 CPUCLKC0
PCICLK6 17
40 GNDCPU
**FS2/PCICLK7 18
39 IREF
GNDPCI 19
**FS3/PCICLK8 20
38 AVDD
37 GND
**SEL100_133#/PCICLK9 21
36 VDD3V66
VDDPCI 22
35 3V66_3
SDATA 23
34 3V66_2
GND48 24
33 GND3V66
*FS0/48MHz_0 25
32 GND3V66
**FS1/48MHz_1 26
31 3V66_1
AVDD48 27
30 3V66_0
PD# 28
29 VDD3V66
56-SSOP
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
0690D—05/14/04

1 page




ICS950703 pdf
Integrated
Circuit
Systems, Inc.
Maximum Allowed Current
Pin Description
Condition
Max 3.3V supply consumption
Max discrete cap loads,
Vdd = 3.465V
All static inputs = Vdd or GND
Powerdown Mode
(PWRDWN# = 0)
40mA
Full Active
360mA
CPUCLK Swing Select Functions
MULTSEL0
0
0
0
0
1
1
1
1
BYTE 1
BIT 3
0
0
1
1
0
0
1
1
Board Target
Trace/Term Z
60 ohms
50 ohms
60 ohms
50 ohms
60 ohms
50 ohms
60 ohms
50 ohms
Reference R,
Iref=
Vdd/(3*Rr)
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Output
Current
Ioh = 4*Iref
Ioh = 4*Iref
Ioh = 6*Iref
Ioh = 6*Iref
Ioh = 5*Iref
Ioh = 5*Iref
Ioh = 7*Iref
Ioh = 7*Iref
0
0
30 (DC equiv)
Rr = 221 1%
Iref = 5mA
Ioh = 5*Iref
0
0
25 (DC equiv)
Rr = 221 1%
Iref = 5mA
Ioh = 5*Iref
0
1
30 (DC equiv)
Rr = 221 1%
Iref = 5mA
Ioh = 6*Iref
0
1
25 (DC equiv)
Rr = 221 1%
Iref = 5mA
Ioh = 6*Iref
1
0
30 (DC equiv)
Rr = 221 1%
Iref = 5mA
Ioh = 4*Iref
1
0
25 (DC equiv)
Rr = 221 1%
Iref = 5mA
Ioh = 4*Iref
1
1
30 (DC equiv)
Rr = 221 1%
Iref = 5mA
Ioh = 7*Iref
1
1
25 (DC equiv)
Rr = 221 1%
Iref = 5mA
Ioh = 7*Iref
Voh @ Z,
Iref=2.32mA
0.56V @ 60
0.47V @ 50
0.85V /2 60
0.71V @ 50
0.71V @ 60
0.59V @ 50
0.99V @ 60
0.82V @ 50
0.75V @ 30
0.62V @ 20
0.90V @ 30
0.75V @ 20
0.60 @ 20
0.5V @ 20
1.05V @ 30
0.84V @ 20
0690D—05/14/04
5
ICS950703

5 Page





ICS950703 arduino
Integrated
Circuit
Systems, Inc.
ICS950703
I2C Table: Frequency Select Register
Byte 0
Pin #
Name
Bit 7
-
FS Source
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
FS6
FS5
FS4
FS3
FS2
FS1
FS0
Control Function
Frequency H/W IIC
Select
Freq Select Bit 6
Freq Select Bit 5
Freq Select Bit 4
Freq Select Bit 3
Freq Select Bit 2
Freq Select Bit 1
Freq Selcet Bit 0
Type
RW
RW
RW
RW
RW
RW
RW
RW
I2C Table: Spreading, Device Behavior and Output Control Register
Byte 1
Pin #
Name
Control Function Type
Bit 7
-
SS1
Spread Select 1
RW
Bit 6
-
SS0
Spread Select 0
RW
Bit 5
-
SSEN
Spread Enable
Control
RW
Bit 4
-
Reserved
Reserved
RW
Bit 3
51/50
CPUT/C3
Output Control
RW
Bit 2
48/47
CPUT/C2
Output Control
RW
Bit 1
45/44
CPUT/C1
Output Control
RW
Bit 0
42/41
CPUT/C0
Output Control
RW
0
Latch
Inputs
1
IIC
See Table 1: Quad
RomTM Frequency
Selection Table
PWD
0
0
0
0
0
0
0
1
01
See Table 2: Spread
Spectrum Table
Disable Enable
-
Disable
Disable
Disable
Disable
-
Enable
Enable
Enable
Enable
PWD
0
0
0
0
1
1
1
1
Table2: Spread Spectrum Select
SS1 SS0
(Byte 1 bit 7)
(Byte 1 bit 6)
00
01
10
11
Spread %
0.35%
0.50%
0.70%
1.00%
Downspread
%
0.32%
0.45%
0.75%
1.00%
Note
Default
Spread 2
Spread 3
Spread 4
I2C Table: Output Control Register
Byte 2
Pin #
Name
Bit 7
18
PCICLK7
Bit 6
17
PCICLK6
Bit 5
15
PCICLK5
Bit 4
14
PCICLK4
Bit 3
12
PCICLK3
Bit 2
11
PCICLK2
Bit 1
9
PCICLK1
Bit 0
8
PCICLK0
Control Function
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
1
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
PWD
1
1
1
1
1
1
1
1
0690D—05/14/04
11

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