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PDF ICS950902 Data sheet ( Hoja de datos )
| Número de pieza | ICS950902 | |
| Descripción | Programmable Timing Control Hub | |
| Fabricantes | Integrated Circuit Systems | |
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Hay una vista previa y un enlace de descarga de ICS950902 (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
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Integrated
Circuit
Systems, Inc.
ICS950902
Programmable Timing Control Hub™ for P4™
Recommended Application:
VIA P4X/P4M/KT/KN266/333 style chipsets.
Output Features:
• 1 - Pair of differential CPU clocks @ 3.3V (CK408)/
1 - Pair of differential open drain CPU clocks (K7)
• 1 - Pair of differential push pull CPU_CS clocks @ 2.5V
• 3 - AGP @ 3.3V
• 7 - PCI @ 3.3V (1 - Free running)
• 1 - 48MHz @ 3.3V fixed
• 1 - 24_48MHz @ 3.3V (Default 48MHz I2C select only)
• 2 - REF @ 3.3V, 14.318MHz
• 12 - SDRAM (6 pair - DDR) selectable
Key Specifications:
• CPU_CS - CPUT/C: <±250ps
• CPU_CS - AGP: <±250ps
• CPU - DDR/SD: <±250ps
• PCI - PCI: <500ps
• CPU - PCI: Min = 1.0ns, Typ = 2.0ns, Max = 4.0ns
Features/Benefits:
• Programmable output frequency.
• Programmable output divider ratios.
• Programmable output rise/fall time.
• Programmable output skew.
• Programmable spread percentage for EMI control.
• DDR output buffer supports up to 200MHz.
• Watchdog timer technology to reset system
if system malfunctions.
• Programmable watch dog safe frequency.
• Support I2C Index read/write and block read/write
operations.
• Uses external 14.318MHz crystal.
Frequency Table
FS3
FS2
FS1
FS0
CPUCLK
MHz
AGP
MHz
0 0 0 0 160.00 80.00
0 0 0 1 164.00 82.00
0 0 1 0 166.60 66.60
0 0 1 1 170.00 68.00
0 1 0 0 175.00 70.00
0 1 0 1 180.00 72.00
0 1 1 0 185.00 74.00
0 1 1 1 190.00 76.00
1 0 0 0 66.80 66.80
1 0 0 1 100.90 67.27
1 0 1 0 133.60 66.80
1 0 1 1 200.40 66.80
1 1 0 0 66.60 66.60
1 1 0 1 100.00 66.60
1 1 1 0 200.00 66.60
1 1 1 1 133.30 66.60
PCICLK
MHz
40.00
41.00
33.30
34.00
35.00
36.00
37.00
38.00
33.40
33.63
33.40
33.40
32.30
33.30
33.30
33.30
MULTISEL0
Board Target
Trace/Term Z
0 50 ohms
1 50 ohms
Reference R,
Iref =
VDD/(3*Rr)
Rr = 221 1%,
Iref = 5.00mA
Rr = 475 1%,
Iref = 2.32mA
Output
Current
Voh @ Z
Ioh = 4* I REF 1.0V @ 50
Ioh = 6* I REF 0.7V @ 50
0475G—03/23/04
Pin Configuration
*FS0/REF0 1
GND 2
X1 3
X2 4
VDDAGP 5
*MODE/AGPCLK0 6
*SEL_408/K7/AGPCLK1 7
*(PCI_STOP#)AGPCLK2 8
GNDAGP 9
**FS1/PCICLK_F 10
**SEL_SDR/DDR#/PCICLK1 11
*MULTSEL/PCICLK2 12
GNDPCI 13
PCICLK3 14
PCICLK4 15
VDDPCI 16
PCICLK5 17
*(CLK_STOP#)PCICLK6 18
GND48 19
*FS3/48MHz 20
*FS2/24_48MHz 21
AVDD48 22
VDD 23
GND 24
IREF 25
*(PD#)RESET# 26
SCLK 27
SDATA 28
56 Vtt_PWRGD#**/REF1
55 VDDREF
54 GND
53 CPUCLKT/CPUCLKODT
52 CPUCLKC/CPUCLKODC
51 VDDCPU3.3
50 VDDCPU2.5
49 CPUC_CS
48 CPUT_CS
47 GND
46 FBOUT
45 BUF_IN
44 DDRT0/SDRAM0
43 DDRC0/SDRAM1
42 DDRT1/SDRAM2
41 DDRC1/SDRAM3
40 VDD3.3_2.5
39 GND
38 DDRT2/SDRAM4
37 DDRC2/SDRAM5
36 DDRT3/SDRAM6
35 DDRC3/SDRAM7
34 VDD3.3_2.5
33 GND
32 DDRT4/SDRAM8
31 DDRC4/SDRAM9
30 DDRT5/SDRAM10
29 DDRC5/SDRAM11
56-Pin 300-mil SSOP & 240-mil TSSOP
* Internal 120K pull-up resistor to VDD.
** Internal 120K pull-down resistor to GND.
1 page  
Integrated
Circuit
Systems, Inc.
ICS950902
General I2C serial interface information
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will acknowledge
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
(see Note 2)
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte
location = N
• ICS clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D3 (H)
• ICS clock will acknowledge
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host)
T starT bit
ICS (Slave/Receiver)
Slave Address D2(H)
WR WRite
ACK
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
ACK
Byte N + X - 1
P stoP bit
ACK
*See notes on the following page.
0475G—03/23/04
5
Index Block Read Operation
Controller (Host)
ICS (Slave/Receiver)
T starT bit
Slave Address D2(H)
WR WRite
ACK
Beginning Byte = N
ACK
RT Repeat starT
Slave Address D3(H)
RD ReaD
ACK
ACK
ACK
Data Byte Count = X
Beginning Byte N
N Not acknowledge
P stoP bit
Byte N + X - 1
5 Page 
Integrated
Circuit
Systems, Inc.
ICS950902
Byte 17: Output Divider Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
AGP_INV
Reserved
CPU_INV
CPU_INV
PCI Div 3
PCI Div 2
PCI Div 1
PCI Div 0
PWD
Description
0 AGP Phase Inversion bit
0 Reserved
0 CPU T/C Phase Inversion bit
0 CPUT/C_CS Phase Inversion bit
1
0
0
PCI clock divider ratio can be configured via these 4 bits
individually. For divider selection table refer to Table 2.
Default at power up is latched FS divider.
1
Table 1
Div (3:2)
00 01 10 11
Div (1:0)
00 /2 /4 /8 /16
01 /3 /6 /12 /24
10 /5 /10 /20 /40
11 /7 /14 /28 /56
Table 2
Div (3:2)
00 01 10 11
Div (1:0)
00 /4 /8 /16 /32
01 /3 /6 /12 /24
10 /5 /10 /20 /40
11 /9 /18 /36 /72
Byte 18: Group Skew Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
CPUCLKT/C_CS
Group Skew
Control
CPUCLKT/C
Group Skew
Control
AGPCLK
Group Skew
Control
Reserved
Reserved
PWD
1
0
1
0
1
0
X
X
Description
These 2 bits delay the CPUCLKT/C_CS with respect to
CPUCLKT/C_CS
00 = 0ps 01 = 250ps 10 = 500ps 11 =750ps
These 2 bits delay the CPUCLKT/C clock with respect to
CPUCLKT/C_CS
00 = 0ps 01 = 250ps 10 = 500ps 11 = 750ps
These 2 bits delay the AGPCLK clocks with respect to CPUCLK
00 = 0ps 01 = 250ps 10 = 500ps 11 = 750ps
Reserved
Reserved
Byte 19: Group Skew Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reserved
PCICLK(5:0)
Group Skew
Control
PWD
1
0
0
0
1
0
0
0
Description
Reserved
These 4 bits can change the CPU to PCI (5:0) skew from 1.4ns -
2.9ns. Default at power up is - 2.5ns. Each binary increment or
decrement of Bits (3:0) will increase or decrease the delay of the
PCI clocks by 100ps.
0475G—03/23/04
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet ICS950902.PDF ] | |
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