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Número de pieza ICS950905
Descripción Programmable Timing Control Hub
Fabricantes Integrated Circuit Systems 
Logotipo Integrated Circuit Systems Logotipo



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Integrated
Circuit
Systems, Inc.
ICS950905
Advance Information
Programmable Timing Control Hub™ for P4™
Recommended Application:
VIA P4X266 chipset with PC133 or DDR memory.
Output Features:
• 2 - Pair of differential CPU clocks @ 3.3V
• 1 - Pair of differential push pull CPU_CS clocks @ 2.5V
• 3 - AGP @ 3.3V
• 9 - PCI @ 3.3V
• 1- IOAPIC @ 2.5V
• 1 - 48MHz @ 3.3V fixed
• 1 - 24_48MHz @ 3.3V
• 1 - REF @ 3.3V, 14.318MHz
Features/Benefits:
• Programmable output frequency.
• Programmable output divider ratios.
• Programmable output rise/fall time.
• Programmable output skew.
Pin Configuration
1**SEL24_48/REF0
VDDREF
GND
X1
X2
VDD48
*FS3/48MHz
*FS2/24_48MHz
GND
*FS0/PCICLK_F
**FS1/PCICLK0
*MULTI_SEL/PCICLK1
GND
*WDTB/PCICLK2
**WDEN/PCICLK3
VDDPCI
PCICLK4
PCICLK5
PCICLK6
GND
PCICLK7
*PD#
AGPCLK0
VDDAGP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 VDDLAPIC
47 GND
46 N/C
45 IOAPIC
44 GND
43 VDDCPU_PP (2.5V)
42 CPUCLK_PPT
41 CPUCLK_PPC
40 CPUCLKT_0
39 CPUCLKC_0
38 VDDCPU (3.3V)
37 I REF
36 GND
35 CPUCLKT_1
34 CPUCLKC_1
33 Vtt_PWRGD#
32 CPU_STOP#*
31 PCI_STOP#*
30 RESET#
29 SDATA
28 SCLK
27 AGPCLK2
26 AGPCLK1
25 GND
• Programmable spread percentage for EMI control.
• Watchdog timer technology to reset system
if system malfunctions.
• Programmable watch dog safe frequency.
• Support I2C Index read/write and block read/write
operations.
48-Pin 300-mil SSOP
1. These outputs have 2X drive strength.
* These inputs have a internal Pull-up resistor
of 120K to VDD
** These inputs have a internal pull-down to GND
• For DDR and or PC133 SDRAM system use ICS93718 Frequency Table
as the memory buffer.
• Uses external 14.318MHz crystal.
Key Specifications:
FS3
FS2
FS1
FS0
CPUCLK
MHz
AGP
MHz
PCICLK
MHz
CPU_CS - CPU0: <±250ps
• CPU_CS - AGP: <±250ps
• PCI - PCI: <500ps
• CPU - PCI: Min = 1.0ns, Typ = 2.0ns, Max = 4.0ns
Block Diagram
0 0 0 0 160.00 80.00 40.00
0 0 0 1 164.00 82.00 41.00
0 0 1 0 166.60 66.60 33.30
0 0 1 1 170.00 68.00 34.00
0 1 0 0 175.00 70.00 35.00
PLL2
X1 XTAL
X2 OSC
/2
48MHz
24_48MHz
REF0
0 1 0 1 180.00 72.00 36.00
0 1 1 0 185.00 74.00 37.00
0 1 1 1 190.00 76.00 38.00
1 0 0 0 66.80 66.80 33.40
1 0 0 1 100.90 67.27 33.63
PLL1
Spread
Spectrum
CPU
DIVDER
Stop
CPUCLKT_(1:0)
CPUCLKC_(1:0)
1 0 1 0 133.60 66.80 33.40
1 0 1 1 200.40 66.80 33.40
SEL24_48
SDATA
SCLK
FS (3:0)
PD#
PCI_STOP#
CPU_STOP#
MULTI_SEL
Vtt_PWRGD#
WDEN
WDTB
Control
Logic
Config.
Reg.
CPU
DIVDER
Stop
IOAPIC
DIVDER
PCI
DIVDER
Stop
AGP
DIVDER
CPUCLK_PPT
CPUCLK_PPC
IOAPIC
PCICLK (7:0)
PCICLK_F
AGPCLK (2:0)
3
RESET#
I REF
1 1 0 0 66.60 66.60 32.30
1 1 0 1 100.00 66.60 33.30
1 1 1 0 200.00 68.60 33.30
1 1 1 1 133.30 68.60 33.30
MULTISEL0
Board Target
Trace/Term Z
0 50 ohms
1 50 ohms
Reference R,
Iref =
VDD/(3*Rr)
Rr = 221 1%,
Iref = 5.00mA
Rr = 475 1%,
Iref = 2.32mA
Output
Current
Voh @ Z
Ioh = 4* I REF 1.0V @ 50
Ioh = 6* I REF 0.7V @ 50
950905 Rev - 11/26/01
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.

1 page




ICS950905 pdf
Integrated
Circuit
Systems, Inc.
Byte 1: CPU Active/Inactive Register
(1 = enable, 0 = disable)
Bit Pin# PWD
Description
Bit7 -
1 (Reserved)
Bit6 10
1 PCICLK_F (Active/Inactive)
Bit5 -
1 (Reserved)
Bit4 -
1 (Reserved)
Bit3 -
0 CPUCLKT/C_CS 1x/2x Strength(1 = 2x, 0 = 1x)
Bit2 35, 34
1 CPUCLKT/C1 (Active/Inactive)
Bit1 40, 39
1 CPUCLKT/C0 (Active/Inactive)
Bit0 42, 41
1 CPUCLKT/C_CS (Active/Inactive)
Byte 2: PCI Active/Inactive Register
(1 = enable, 0 = disable)
Bit Pin# PWD
Bit7 21
1 PCICLK7 (Active/Inactive)
Bit6 19
1 PCICLK6 (Active/Inactive)
Bit5 18
1 PCICLK5 (Active/Inactive)
Bit4 17
1 PCICLK4 (Active/Inactive)
Bit3 15
1 PCICLK3 (Active/Inactive)
Bit2 14
1 PCICLK2 (Active/Inactive)
Bit1 12
1 PCICLK1 (Active/Inactive)
Bit0 11
1 PCICLK0 (Active/Inactive)
Description
Byte 3: Active/Inactive Register
(1 = enable, 0 = disable)
Bit Pin# PWD
Description
Bit7 -
1 Reserved
Bit6 1
1 SEL 24_48, 0=24Mhz 1=48MHz
Bit5 -
1 (Reserved)
Bit4 -
- (Reserved)
Bit3 45
1 IOAPIC 1
Bit2 23
1 AGPCLK 0
Bit1 26
1 AGPCLK 1
Bit0 27
1 AGPCLK 2
Byte 4: Frequency Select Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
-
-
-
-
7
8
-
1
PWD
X
X
X
X
1
1
X
1
Latched FS3#
Latched FS2#
Latched FS1#
Latched FS0#
48MHz (Active/Inactive)
24_48MHz (Active/Inactive)
WDEN (Readback)
REF (Active/Inactive)
Description
Third party brands and names are the property of their respective owners.
5
ICS950905
Advance Information

5 Page





ICS950905 arduino
Integrated
Circuit
Systems, Inc.
ICS950905
Advance Information
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +5%
PAR AMETER
SYMBOL
COND ITIONS
MIN TYP MAX
Input High Voltage
Input Low Voltage
Input High Current
Input Low C urrent
Input Low C urrent
VIH
VIL
IIH VIN = VDD
IIL1 VIN = 0 V; Inputs with no pull-up res is tors
IIL2 VIN = 0 V; Inputs with pull-up res is tors
2
VSS- 0 .3
-5
-5
-200
VD D + 0 .3
0 .8
5
Op e ra ti n g
Supply Current
Power Down
Supply Current
IDD 3.3OP
IDD 3.3PD
CL = 0 pF; Select @ 66M
CL = Full load
IR EF=2.32
IR EF= 5m A
100
280
20
37
Input frequency
Fi VDD = 3.3 V;
Pin Inductance
L pi n
7
Input C apacitance1
CIN Logic Inputs
C out Out put pin capacitance
5
6
Trans ition Tim e1
C INX
Ttrans
X1 & X2 pins
To 1s t cros s ing of target Freq.
27 45
3
Settling Tim e1
Clk Stabilization1
Ts
TSTAB
From 1s t cros s ing to 1% target Freq.
From VDD = 3.3 V to 1% target Freq.
3
3
Delay
tPZ H ,tPZ H
tPLZ,tPZH
output enable delay (all outputs )
output dis able delay (all outputs )
1 10
1 10
1Guarenteed by des ign, not 100% tes ted in production.
UN ITS
V
V
mA
mA
mA
mA
mA
mA
mA
MH z
nH
pF
pF
pF
mS
mS
mS
nS
nS
Third party brands and names are the property of their respective owners.
11

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