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PDF ICS950104 Data sheet ( Hoja de datos )
| Número de pieza | ICS950104 | |
| Descripción | Programmable System Clock Chip for PIII Processor | |
| Fabricantes | Integrated Circuit Systems | |
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Integrated
Circuit
Systems, Inc.
ICS950104
Advance Information
Programmable System Clock Chip for PIII™ Processor
Recommended Application:
SIS630ST style chipset
Output Features:
• 1 - CPU clocks @ 2.5V
• 1 - Pair of differential CPU clocks @ 3.3V
• 9 - SDRAM @ 3.3V
• 7 - PCI @3.3V
• 1 - 48MHz, @3.3V
• 1 - 24/48MHz @ 3.3V
• 3 - REF @3.3V, (selectable strength) through I2C
Features:
• Programmable ouput frequency
• Programmable ouput rise/fall time
• Programmable CPU, SDRAM, and PCI skew
• Real time system reset output
• Spread spectrum for EMI control typically
by 7dB to 8dB, with programmable spread percentage
• Watchdog timer technology to reset system
if over-clocking causes malfunction
• Uses external 14.318MHz crystal
Skew Specifications:
• CPU - CPU: <250ps
• PCI - PCI: <500ps
• SDRAM - SDRAM: <250ps
• CPU - SDRAM:<350ps
• CPU - PCI: <3ns
Block Diagram
PLL2
X1 XTAL
X2 OSC
PLL1
Spread
Spectrum
SDATA
SCLK
FS(3:0)
PD#
PCI_STOP#
CPU_STOP#
MODE
MULTSEL
Control
Logic
Config.
Reg.
/2
CPU
DIVDER
Stop
SDRAM
DIVDER
Stop
PCI
DIVDER
Stop
48MHz
24_48MHz
3 REF(2:0)
CPUCLKT0
CPUCLKC0
CPUCLK
10 SDRAM (9:0)
6 PCICLK (5:0)
PCICLK_F
Pin Configuration
CPUCLKC0
CPUCLKT0
VDDCPU
GND
AVDD
X1
X2
**FS0/REF0
VDDREF
**FS1/REF1
REF2
GND
*FS2/PCICLK_F
PCICLK0
PCICLK1
PCICLK2
GND
VDDPCI
PCICLK3
PCICLK4
PCICLK5
AVDD48
**MULTSEL/24_48MHz
**FS3/48MHz
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
GND
IREF
GND
CPUCLK
VDDL
SDATA
SDRAM_STOP#*
SDRAM0
SDRAM1
SDRAM2
SDRAM3
VDD
GND
SDRAM4
SDRAM5
SDRAM6
SDRAM7
GND
VDD
PCI_STOP#*
CPU_STOP#*
PD#/Vtt_PWRGD#*
SCLK
GND
48-Pin 300mil SSOP
Notes:
REF0 can be 1X or 2X strength controlled by I2C.
* Internal Pull-up Resistor of 120K to VDD
** Internal Pull-down of 120K to GND
Functionality
FS3 FS2
FS1
FS0
CPU
(MHz)
SDRAM
(MHz)
PCICLK
(MHz)
0 0 0 0 66.6
100.0
33.3
0 0 0 1 100.0 100.0
33.3
0 0 1 0 150.0 100.0
37.5
0 0 1 1 133.3 100.0
33.3
0 1 0 0 66.8
133.6
33.4
0 1 0 1 100.0 133.3
33.3
0 1 1 0 100.0 150.0
37.5
0 1 1 1 133.3 133.3
33.3
1 0 0 0 66.8
66.8
33.4
1 0 0 1 97.0
97.0
32.3
1 0 1 0 70.0
105.0
35.0
1 0 1 1 95.0
95.0
31.7
1 1 0 0 95.0
126.7
31.7
1 1 0 1 112.0 112.0
37.3
1 1 1 0 97.0
129.3
32.2
1 1 1 1 96.2
96.2
32.1
950104 Rev - 09/11/01
Third party brands and names are the property of their respective owners.
ADVANCE INFORMATION documents contain information on products
in the formative or design phase development. Characteristic data and
other specifications are design goals. ICS reserves the right to change or
discontinue these products without notice.
1 page  
ICS950104
Advance Information
Brief I2C registers description for ICS950104
Programmable System Frequency Generator
Register Name
Functionality & Frequency
Select Register
Output Control Registers
Byte
0
1-6
D es crip tion
Output frequency, hardware / I2C
frequency select, spread spectrum &
output enable control register.
Active / inactive output control
registers/latch inputs read back.
PWD Default
See individual
byte description
See individual
byte description
Vendor ID & Revision ID
R egis ters
7
Byte 11 bit[7:4] is ICS vendor id - 1001.
Other bits in this register designate device
revision ID of this part.
See individual
byte description
Byte Count
Read Back Register
Writing to this register will configure
8 byte count and how many byte will be
read back. Do not write 00H to this byte.
08H
Watchdog Timer
Count Register
Writing to this register will configure the
9 number of seconds for the watchdog
timer to reset.
10H
Watchdog Control Registers 10 Bit [6:0]
VCO Control Selection Bit 10 Bit [7]
Watchdog enable, watchdog status and
programmable 'safe' frequency' can be
configured in this register.
This bit select whether the output
frequency is control by hardware/byte 0
configurations or byte 11&12
programming.
000,0000
0
VCO Frequency Control
R egis ters
11-12
These registers control the dividers ratio
into the phase detector and thus control
the VCO output frequency.
Depended on
hardware/byte 0
configuration
Spread Spectrum Control
R egis ters
13-14
These registers control the spread
percentage amount.
Depended on
hardware/byte 0
configuration
Group Skews Control
R egis ters
15-16
Increment or decrement the group skew
amount as compared to the initial skew.
See individual
byte description
Output Rise/Fall Time
Select Registers
17-20
These registers will control the output
rise and fall time.
See individual
byte description
Notes:
1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Readback will support standard SMBUS controller protocol. The number of bytes to readback is
defined by writing to byte 8.
2. When writing to byte 11 - 12, and byte 13 - 14, they must be written as a set. If for example, only byte 14 is written
but not 15, neither byte 14 or 15 will load into the receiver.
3. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
4. The input is operating at 3.3V logic levels.
5. The data byte format is 8 bit bytes.
6. To simplify the clock generator I2C interface, the protocol is set to use only Block-Writes from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete
byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored
for those two bytes. The data is loaded until a Stop sequence is issued.
7. At power-on, all registers are set to a default condition, as shown.
Third party brands and names are the property of their respective owners.
5
5 Page 
ICS950104
Advance Information
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70º C; Supply Voltage VDD = 3.3V, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Input High Voltage
VIH
Input Low Voltage
VIL
Input High Current
IIH VIN = VDD
Input Low Current
IIL1 VIN = 0 V; Inputs with no pull-up resistors
Input Low Current
IIL2 VIN = 0 V; Inputs with pull-up resistors
Operating
IDD3.3OP66 CL = 0 pF; Select @ 66MHz
Supply Current
IDD3.3OP100 CL = 0 pF; Select @ 100MHz
Input frequency
Input Capacitance1
Fi VDD = 3.3 V;
CIN Logic Inputs
Clk Stabilization1
CINX
TSTAB
X1 & X2 pins
From VDD = 3.3 V to 1% target Freq.
1Guaranteed by design, not 100% tested in production.
2
VSS-0.3
-5
-200
12
27
VDD+0.3
0.8
5
V
V
µA
µA
µA
77
100 mA
16 MHz
5 pF
45 pF
3 ms
Third party brands and names are the property of their respective owners.
11
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| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet ICS950104.PDF ] | |
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