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PDF ICS950201 Data sheet ( Hoja de datos )
| Número de pieza | ICS950201 | |
| Descripción | Programmable Timing Control Hub for P4 | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
ICS950201
Programmable Timing Control Hub™ for P4™
Recommended Application:
CK-408 clock for Intel® 845 chipset with P4 processor.
Output Features:
• 3 Differential CPU Clock Pairs @ 3.3V
• 7 PCI (3.3V) @ 33.3MHz
• 3 PCI_F (3.3V) @ 33.3MHz
• 1 USB (3.3V) @ 48MHz
• 1 DOT (3.3V) @ 48MHz
• 1 REF (3.3V) @ 14.318MHz
• 5 3V66 (3.3V) @ 66.6MHz
• 1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz
Features:
• Supports spread spectrum modulation,
down spread 0 to -0.5%.
• Efficient power management scheme through PD#,
CPU_STOP# and PCI_STOP#.
• Uses external 14.318MHz crystal
• Stop clocks and functional control available through
I2C interface.
Key Specifications:
• CPU Output Jitter <150ps
• 3V66 Output Jitter <250ps
• CPU Output Skew <100ps, programmable over 800 ps
with groups CPU0,1 and CPU2.
Pin Configuration
56-Pin SSOP & TSSOP
* These inputs have 150K internal pull-up resistor to VDD.
Block Diagram
Frequency Table
FS2 FS1 FS0
CPU
(MHz)
3V66
(MHz)
66Buff[2:0]
3V66[4:2]
(MHz)
PCI_F
PCI
(MHz)
0 0 0 66.66 66.66
66.66
33.33
0 0 1 100.00 66.66
66.66
33.33
0 1 0 200.00 66.66
66.66
33.33
0 1 1 133.33 66.66
66.66
33.33
Mid 0 0 Tristate Tristate Tristate Tristate
Mid 0 1 TCLK/2 TCLK/4 TCLK/4 TCLK/8
Mid 1 0 Reserved Reserved Reserved Reserved
Mid 1 1 Reserved Reserved Reserved Reserved
0460G—08/31/04
1 page  
Integrated
Circuit
Systems, Inc.
ICS950201
Byte 2: Control Register
Bit
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Pin#
10
11
12
13
16
17
18
-
Name
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
PCICLK6
-
PWD
1
1
1
1
1
1
1
0
Type
RW
RW
RW
RW
RW
RW
RW
-
Description
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
(Reserved)
Byte 3: Control Register
Bit
Bit 0
Bit 1
Bit 2
Pin#
5
6
7
Name
PCICLK_F0
PCICLK_F1
PCICLK_F2
Bit 3 5 PCICLK_F0
Bit 4 6 PCICLK_F1
Bit 5
Bit 6
Bit 7
7 PCICLK_F2
39 48MHz_USB
38 48MHz_DOT
PWD
1
1
1
0
0
0
1
1
Type
RW
RW
RW
RW
RW
RW
RW
RW
Description
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
Allow control of PCICLK_F0 with assertion of
PCI_STOP#. 0=Free Running, 1=Not free
running
Allow control of PCICLK_F1 with assertion of
PCI_STOP#. 0=Free Running, 1=Not free
running
Allow control of PCICLK_F2 with assertion of
PCI_STOP#. 0=Free Running, 1=Not free
running
0=Disabled 1=Enabled
0=Disabled 1=Enabled
Byte 4: Control Register
Bit
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Pin#
21
22
23
24
35
33
-
-
Name
3V66-2
3V66-3
3V66-4
3V66_5
3V66_1/VCH_CLK
3V66_0
-
-
Notes:
1. R= Read only RW= Read and Write
2. PWD = Power on Default
PWD
1
1
1
1
1
1
0
0
Type
RW
RW
RW
RW
RW
RW
R
R
Description
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
(Reserved)
(Reserved)
0460G—08/31/04
5
5 Page 
Integrated
Circuit
Systems, Inc.
ICS950201
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending first byte (Byte 0)
through byte 5
• ICS clock will acknowledge each byte one at a
time.
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the read address D3 (H)
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• ICS clock sends first byte (Byte 0) through byte 6
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
How to Write:
Controller (Host)
Start Bit
Address
D 2(H )
Dummy Command Code
Dummy Byte Count
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Stop Bit
ICS (Slave/Receiver)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
How to Read:
Controller (Host)
Start Bit
Address
D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Stop Bit
ICS (Slave/Receiver)
ACK
Byte Count
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Notes:
1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3. The input is operating at 3.3V logic levels.
4. The data byte format is 8 bit bytes.
5. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes
must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been
transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes.
The data is loaded until a Stop sequence is issued.
6. At power-on, all registers are set to a default condition, as shown.
0460G—08/31/04
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ICS950201.PDF ] | |
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