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PDF ICS950202 Data sheet ( Hoja de datos )
| Número de pieza | ICS950202 | |
| Descripción | Programmable Timing Control Hub for P4 | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
ICS950202
Programmable Timing Control HubTM for P4TM
Recommended Application:
CK-408 clock for Intel® 845 chipset.
Output Features:
• 3 - Pairs of differential CPU clocks @ 3.3V
• 3 - 3V66 @ 3.3V
• 9 - PCI @ 3.3V
• 2 - 48MHz @ 3.3V fixed
• 1 - VCH/3V66 @ 3.3V, 48MHz or 66MHz
• 1 - REF @ 3.3V, 14.318MHz
Features/Benefits:
• Programmable output frequency.
• Programmable output divider ratios.
• Programmable output rise/fall time.
• Programmable output skew.
• Programmable spread percentage for EMI control.
• Watchdog timer technology to reset system
if system malfunctions.
• Programmable watch dog safe frequency.
• Support I2C Index read/write and block read/write
operations.
• Uses external 14.318MHz crystal.
Key Specifications:
• CPU Output Jitter <150ps
• 3V66 Output Jitter <250ps
• CPU Output Skew <100ps
Pin Configuration
VDDREF
X1
X2
GND
1**FS0/PCICLK7
1**FS1/PCICLK8
VDDPCI
GND
1*WDEN/PCICLK0
PCICLK1
PCICLK2
PCICLK3
VDDPCI
GND
PCICLK4
PCICLK5
PCICLK6
VDD3V66
GND
3V66_1
3V66_2
3V66_3
#RESET
VDDA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 REF/FS2**1
47 CPUCLKT0
46 CPUCLKC0
45 VDDCPU
44 CPUCLKT1
43 CPUCLKC1
42 GND
41 VDDCPU
40 CPUCLKT2
39 CPUCLKC2
38 MULTISEL0*
37 I REF
36 GND
35 48MHz_USB/FS3**
34 48MHz_DOT
33 AVDD48
32 GND
31 3V66_0/VCH_CLK/FS4**
30 VDD3V66
29 GND
28 SCLK
27 SDATA
26 Vtt_PWRGD/PD#
25 GND
48-Pin 300-mil SSOP
1. These outputs have 2X drive strength.
* Internal Pull-up resistor of 120K to VDD
** these inputs have 120K internal pull-down
to GND
Block Diagram
0461L—05/28/03
Frequency Table
FS4
FS3
FS2
FS1
FS0
CPUCLK
MHz
3V66
MHz
PCICLK
MHz
0 0 0 0 1 100.00 66.67 33.33
1 0 0 0 1 133.33 66.67 33.33
1 1 1 1 0 66.67 66.67 33.34
1 1 1 1 1 200.00 66.67 33.33
For additional frequency selections please refer to Byte 0.
Power Groups
VDDA = Analog Core PLL
VDDREF = REF, Xtal
AVDD48 = 48MHz
1 page  
Integrated
Circuit
Systems, Inc.
ICS950202
Byte 0: Functionality and frequency select register (Default=0)
Bit Description
Bit
(2,7:4)
Bit 3
Bit 1
Bit 0
Bit2 Bit7 Bit6 Bit5 Bit4 CPUCLK 3V66 PCICLK
FS4 FS3 FS2 FS1 FS0 MHz MHz MHz
Spread %
0 0 0 0 0 100.90 67.27 33.63 +/-0.35% center spread
0 0 0 0 1 100.00 66.67 33.33 0 to -0.6% down spread
0 0 0 1 0 103.00 68.67 34.33 +/-0.35% center spread
0 0 0 1 1 105.00 70.00 35.00 +/-0.35% center spread
0 0 1 0 0 107.00 71.33 35.67 +/-0.35% center spread
0 0 1 0 1 109.00 72.67 36.33 +/-0.35% center spread
0 0 1 1 0 111.00 74.00 37.00 +/-0.35% center spread
0 0 1 1 1 114.00 76.00 38.00 +/-0.35% center spread
0 1 0 0 0 117.00 78.00 39.00 +/-0.35% center spread
0 1 0 0 1 120.00 80.00 40.00 +/-0.35% center spread
0 1 0 1 0 127.00 84.67 42.33 +/-0.35% center spread
0 1 0 1 1 130.00 86.67 43.33 +/-0.35% center spread
0 1 1 0 0 133.33 88.89 44.44 +/-0.35% center spread
0 1 1 0 1 170.00 56.67 28.33 +/-0.35% center spread
0 1 1 1 0 180.00 60.00 30.00 +/-0.35% center spread
0 1 1 1 1 190.00 63.33 31.67 +/-0.35% center spread
1 0 0 0 0 133.90 66.95 33.48 +/-0.35% center spread
1 0 0 0 1 133.33 66.67 33.33 0 to -0.6% down spread
1 0 0 1 0 120.00 60.00 30.00 +/-0.35% center spread
1 0 0 1 1 125.00 62.50 31.25 +/-0.35% center spread
1 0 1 0 0 134.90 67.45 33.73 +/-0.35% center spread
1 0 1 0 1 137.00 68.50 34.25 +/-0.35% center spread
1 0 1 1 0 139.00 69.50 34.75 +/-0.35% center spread
1 0 1 1 1 141.00 70.50 35.25 +/-0.35% center spread
1 1 0 0 0 143.00 71.50 35.75 +/-0.35% center spread
1 1 0 0 1 145.00 72.50 36.25 +/-0.35% center spread
1 1 0 1 0 150.00 75.00 37.5 +/-0.35% center spread
1 1 0 1 1 155.00 77.50 38.75 +/-0.35% center spread
1 1 1 0 0 160.00 80.00 40.00 +/-0.35% center spread
1 1 1 0 1 170.00 85.00 42.50 +/-0.35% center spread
1 1 1 1 0 66.67 66.67 33.34 0 to -0.6% down spread
1 1 1 1 1 200.00 66.67 33.33 0 to -0.6% down spread
0 - Frequency is selected by hardware select, latched inputs
1 - Frequency is selected by Bit 2,7:4
0 - Normal
1 - Spread spectrum enable
0 - Watch dog safe frequency will be selected by latch inputs
1 - Watch dog safe frequency will be programmed by Byte 10 bit (4:0)
PWD
Note 1
0
1
0
Notes:
1. Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
0461L—05/28/03
5
5 Page 
Integrated
Circuit
Systems, Inc.
ICS950202
Byte 20: Group Skew Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
PCI_Skew 3
PCI_Skew 2
PCI_Skew 1
PCI_Skew 0
Reserved
Reserved
Reserved
Reserved
PWD
1
0
0
0
1
0
0
0
Description
These 4 bits can change the CPU to PCI (8:0) skew from 2.2ns
0.7ns. Default at power up is 0.5ns. Each binary increment or
decrement of Bits (3:0) will increase or decrease the delay of the
PCI clocks by 100ps.
Reserved
Reserved
Reserved
Reserved
Byte 21: Slew Rate Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
PCICLK8 Slew 1
PCICLK8 Slew 0
PCICLK7 Slew 1
PCICLK7 Slew 0
3V66 (3:1)_Slew 1
3V66 (3:1)_Slew 1
3V66_0_Slew 1
3V66_0_Slew 0
PWD
1
0
1
0
1
0
1
0
Description
PCICLK8 clock slew rate control bits.
01 = strong: 11 = normal; 10 = weak
PCICLK7 clock slew rate control bits.
01 = strong: 11 = normal; 10 = weak
3V66 (3:1) clock slew rate control bits.
01 = strong: 11 = normal; 10 = weak
3V66_0 clock slew rate control bits.
01 = strong: 11 = normal; 10 = weak
Byte 22: Slew Rate Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
REF Slew 1
REF Slew 0
PCI (6:4) Slew 1
PCI (6:4) Slew 0
PCI (3:1) Slew 1
PCI (3:1) Slew 0
PCI0 Slew 1
PCI0 Slew 0
PWD
1
0
1
0
1
0
1
0
Description
REF clock slew rate control bits.
01 = strong: 11 = normal; 10 = weak
PCI (6:4) clock slew rate control bits.
01 = strong: 11 = normal; 10 = weak
PCI (3:1) clock slew rate control bits.
01 = strong: 11 = normal; 10 = weak
PCI0 clock slew rate control bits.
01 = strong: 11 = normal; 10 = weak
Byte 23: Slew Rate Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reserved
Reserved
VCH Slew 1
VCH Slew 0
48USB Slew 1
48USB Slew 0
48DOT Slew 1
48DOT Slew 0
PWD
X
X
1
0
1
0
1
0
Description
Reserved
VCH clock slew rate control bits.
01 = strong: 11 = normal; 10 = weak
48USB clock slew rate control bits.
01 = strong: 11 = normal; 10 = weak
48DOT clock slew rate control bits.
01 = strong: 11 = normal; 10 = weak
0461L—05/28/03
11
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet ICS950202.PDF ] | |
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