DataSheet.es    


PDF ICS950223 Data sheet ( Hoja de datos )

Número de pieza ICS950223
Descripción Programmable Timing Control Hub for P4
Fabricantes Integrated Circuit Systems 
Logotipo Integrated Circuit Systems Logotipo



Hay una vista previa y un enlace de descarga de ICS950223 (archivo pdf) en la parte inferior de esta página.


Total 24 Páginas

No Preview Available ! ICS950223 Hoja de datos, Descripción, Manual

Integrated
Circuit
Systems, Inc.
ICS950223
Programmable Timing Control Hub™ for P4
Recommended Application:
Pin Configuration
Brookdale and Brookdale-G chipset with P4 processor.
Output Features:
• 3 - Pairs of differential CPU clocks
(differential current mode)
*MULTSEL1/REF1 1
VDDREF 2
X1 3
X2 4
48 REF0/MULTSEL0**
47 GNDREF
46 VDDCPU
45 CPUCLKT2
• 3 - 3V66 @ 3.3V
• 10 - PCI @ 3.3V
• 1 - 48MHz @ 3.3V fixed
GND 5
*FS2/PCICLK0 6
*FS3/PCICLK1 7
**SEL48_24#/PCICLK2 8
44 CPUCLKC2
43 GNDCPU
42 PD#*
41 CPUCLKT0
• 2 - REF @ 3.3V, 14.318MHz
• 1 - 48_66MHz selectable @ 3.3V fixed
• 1 - 24_48MHz selectable @ 3.3V
VDDPCI 9
*FS4/PCICLK3 10
PCICLK4 11
PCICLK5 12
40 CPUCLKC0
39 VDDCPU
38 CPUCLKT1
37 CPUCLKC1
GND 13
36 GNDCPU
PCICLK6 14
35 IREF
Features/Benefits:
• QuadRomTM frequency selection.
• Programmable output frequency.
• Programmable asynchronous 3V66 & PCI frequency.
• Programmable output divider ratios.
• Programmable output rise/fall time.
PCICLK7 15
PCICLK8 16
PCICLK9 17
VDDPCI 18
Vttpwr_GD# 19
RESET# 20
GND 21
~*FS0/48MHz 22
34 AVDD
33 GND
32 VDD3V66
31 3V66_0
30 3V66_1
29 GND
28 3V66_2
27 3V66_3_48MHz/Sel66_48#**
• Programmable output skew.
• Programmable spread percentage for EMI control.
• Watchdog timer technology to reset system
if system malfunctions.
*FS1/24_48MHz 23
26 SCLK
AVDD48 24
25 SDATA
48-SSOP
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
• Programmable watchdog safe frequency.
~ This output has 2X drive strength
• Support I2C Index read/write and block read/write
operations.
• Uses external 14.318MHz reference input.
Frequency Table
Bit4 Bit3 Bit2 Bit1 Bit0 CPU
FS4 FS3 FS2 FS1 FS0 MHz
3V66
MHz
PCI
MHz
0 0 0 0 0 102.00 68.00 34.00
Key Specifications:
CPU Output Jitter <150ps
• 3V66 Output Jitter <250ps
• CPU Output Skew <100ps
0 0 0 0 1 105.00 70.00 35.00
0 0 0 1 0 108.00 72.00 36.00
0 0 0 1 1 111.00 74.00 37.00
0 0 1 0 0 114.00 76.00 38.00
0 0 1 0 1 117.00 78.00 39.00
0 0 1 1 0 120.00 80.00 40.00
Block Diagram
0 0 1 1 1 123.00 82.00 41.00
0 1 0 0 0 126.00 72.00 36.00
0 1 0 0 1 130.00 74.29 37.14
PLL2
X1 XTAL
X2 OSC
/2
48MHz
24_48MHz
REF (1:0)
0 1 0 1 0 136.00 68.00 34.00
0 1 0 1 1 140.00 70.00 35.00
0 1 1 0 0 144.00 72.00 36.00
0 1 1 0 1 148.00 74.00 37.00
0 1 1 1 0 152.00 76.00 38.00
3V66
DIVDER
3V66_48MHz
0 1 1 1 1 156.00 78.00 39.00
1 0 0 0 0 160.00 80.00 40.00
PD#
MULTSEL(1:0)
FS (4:0)
SDATA
SCLK
Vtt_PWRGD#
SEL 48_24#
SEL 66_48#
PLL1
Spread
Spectrum
Control
Logic
Config.
Reg.
CPU
DIVDER
PCI
DIVDER
3V66
DIVDER
3 CPUCLKT (2:0)
3 CPUCLKC (2:0)
PCICLK (9:0)
10
3V66 (2:0)
4
RESET#
I REF
1 0 0 0 1 164.00 82.00 41.00
1 0 0 1 0 166.60 66.64 33.32
1 0 0 1 1 170.00 68.00 34.00
1 0 1 0 0 175.00 70.00 35.00
1 0 1 0 1 180.00 72.00 36.00
1 0 1 1 0 185.00 74.00 37.00
1 0 1 1 1 190.00 76.00 38.00
1 1 0 0 0 66.80 66.80 33.40
1 1 0 0 1 100.20 66.80 33.40
1 1 0 1 0 133.60 66.80 33.40
1 1 0 1 1 200.40 66.80 33.40
1 1 1 0 0 66.67 66.67 33.34
1 1 1 0 1 100.00 66.67 33.33
0496C—05/06/05
1 1 1 1 0 200.00 66.67 33.33
1 1 1 1 1 133.33 66.67 33.33

1 page




ICS950223 pdf
Integrated
Circuit
Systems, Inc.
ICS950223
General I2C serial interface information
How to Write:
Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will acknowledge
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
(see Note 2)
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte
location = N
• ICS clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D3 (H)
• ICS clock will acknowledge
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host)
T starT bit
ICS (Slave/Receiver)
Slave Address D2(H)
WR WRite
Beginning Byte = N
Data Byte Count = X
Beginning Byte N
ACK
ACK
ACK
ACK
Byte N + X - 1
P stoP bit
ACK
*See notes on the following page.
0496C—05/06/05
5
Index Block Read Operation
Controller (Host)
T starT bit
ICS (Slave/Receiver)
Slave Address D2(H)
WR WRite
Beginning Byte = N
RT Repeat starT
ACK
ACK
Slave Address D3(H)
RD ReaD
ACK
ACK
ACK
Data Byte Count = X
Beginning Byte N
N Not acknowledge
P stoP bit
Byte N + X - 1

5 Page





ICS950223 arduino
Integrated
Circuit
Systems, Inc.
ICS950223
I2C Table: Output Control Register
Byte 3
Pin #
Name
Control Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
23
24_48MHz
Output Control
22
48MHz
Output Control
-
GR_EN
Geashift Reset Enable
-
24_48 FS Source
24_48 Frequency H/W
/ IIC Select
-
FS 24_48
Sel24_48
8
PCICLK2
Output Control
7
PCICLK1
Output Control
6
PCICLK0
Output Control
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Disable
Disable
ON
Latch Inputs
24MHz
Disable
Disable
Disable
1
Enable
Enable
OFF
IIC
48MHz
Enable
Enable
Enable
PWD
1
1
0
0
0
1
1
1
I2C Table: Output Control Register
Byte 4
Pin #
Name
Control Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
- 66_48 FS Source 66_48 Frequency H/W
/ IIC Select
-
FS 66_48#
Sel66_48#
31
3V66_0
Output Control
30
3V66_1
Output Control
48
REF0
Output Control
1
REF1
Output Control
27
3V66_3
Output Control
28
3V66_2
Output Control
Type
RW
RW
RW
RW
RW
RW
RW
RW
01
Latch Inputs
48MHz
Disable
Disable
Disable
Disable
Disable
Disable
IIC
66.66MHz
Enable
Enable
Enable
Enable
Enable
Enable
PWD
0
0
1
1
1
1
1
1
I2C Table: 3V66 & PCICLK Asynchronous Frequency Control Register
Byte 5
Pin #
Name
Control Function
Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
N PLL2 Div0
N PLL2 Div1
N PLL2 Div2
N PLL2 Div3
N PLL2 Div4
N PLL2 Div5
N PLL2 Div6
N PLL2 Div7
The decimal
representation of N
PLL2 Div (0:7) + 8 is
equal to VCO divider
value for PLL2.
RW
RW
RW
RW
RW
RW
RW
RW
0
-
-
-
-
-
-
-
-
1 PWD
-X
-X
-X
-X
-X
-X
-X
-X
I2C Table: Read Back Register
Byte 6
Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0496C—05/06/05
-
-
-
-
-
-
-
-
WDHRB
SEL48_24RB
SEL66_48RB
FS4RB
FS3RB
FS2RB
FS1RB
FS0RB
Control Function
WD Hard Alarm Status
Read back
Sel48_24# Read Back
Sel66_48# Read Back
FS4 Read back
FS3 Read back
FS2 Read back
FS1 Read back
FS0 Read back
Type
R
R
R
R
R
R
R
R
11
0
-
-
-
-
-
-
-
1 PWD
-X
-X
-X
-X
-X
-X
-X
-X

11 Page







PáginasTotal 24 Páginas
PDF Descargar[ Datasheet ICS950223.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
ICS950223Programmable Timing Control Hub for P4Integrated Circuit Systems
Integrated Circuit Systems
ICS950227Programmable Timing Control Hub for P4Integrated Circuit Systems
Integrated Circuit Systems

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar