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PDF ICS950401 Data sheet ( Hoja de datos )
| Número de pieza | ICS950401 | |
| Descripción | AMD - K8 System Clock Chip | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
ICS950401
AMD - K8™ System Clock Chip
Recommended Application:
AMD K8 Systems
Output Features:
• 2 - Differential pair push-pull CPU clocks @ 3.3V
• 7 - PCI (Including 1 free running) @3.3V
• 3 - Selectable HT/PCI 66/33MHz @3.3V
• 1 - 48MHz, @3.3V fixed.
• 1 - 24/48MHz @ 3.3V
• 3 - REF @3.3V, 14.318MHz.
Features:
• Up to 220MHz frequency support
• Support power management: PCI stop and stop
clocks controlled by I2C.
• Spread spectrum for EMI reduction
• Uses external 14.318MHz crystal
• I2C programmability features
• Supports Hypes transport technology (HT66 output).
Pin Configuration
*FS0/REF0 1
VDDREF 2
X1 3
X2 4
GND 5
*PCI33/HT66SEL# 6
PCICLK33/HT66_0 7
PCICLK33/HT66_1 8
VDDPCI 9
GND 10
PCICLK33/HT66_2 11
NC 12
PCICLK0 13
PCICLK1 14
GND 15
VDDPCI 16
PCICLK2 17
PCICLK3 18
VDDPCI 19
GND 20
PCICLK4 21
PCICLK5 22
PCICLK_F 23
*PCI_STOP# 24
48 REF1/FS1*
47 GND
46 VDDREF
45 REF2/FS2*
44 SPREAD*
43 VDDA
42 GNDA
41 CPUCLKT0
40 CPUCLKC0
39 GND
38 VDDCPU
37 CPUCLKT1
36 CPUCLKC1
35 VDD
34 GND
33 GNDA
32 VDDA
31 48MHz
30 GND
29 VDD
28 24_48MHz/Sel24_48#*
27 GND
26 SDATA
25 SCLK
48-SSOP/ TSSOP
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
Block Diagram
PLL2
X1 XTAL
X2 OSC
/2
PLL1
Spread
Spectrum
CPU
DIVDER
Stop
SDATA
SCLK
FS (2:0)
PCI33/HT66SEL#
PCI_STOP#
SPREAD
24_48SEL#
Control
Logic
Config.
Reg.
PCI
DIVDER
Stop
X2
48MHz
24_48MHz
REF (2:0)
CPUCLKC (1:0)
CPUCLKT (1:0)
Functionality
PCI33_HT66
FS2 FS1 FS0
SEL#
000
X
001
0
001
1
010
X
011
X
100
X
101
X
110
X
111
X
CPU
Hi-Z
X
X
180.00
220.00
100.00
133.33
166.66
200.00
PCI33
Hi-Z
X/6
X/6
30.00
36.56
33.33
33.33
33.33
33.33
PCI33_HT66 COMMENTS
Hi-Z
X/3
X/6
60.00
73.12
33.33/66.66
33.33/66.66
33.33/66.66
33.33/66.66
Tri-State Mode
Bypass Mode
Bypass Mode
10% under-clk
10% over-clk
Athlon Compatible
Athlon Compatible
Reserved
Hammer Operation
PCICLK (5:0)
PCICLK_F
PCICLK33/HT66(2:0)
0499C—11/01/04
1 page  
ICS950401
Byte0: Functionality and Frequency Select
Bit Pin # PWD
Description
7 0 Write disable (Write once)1
6
0
Spread Spectrum Enable. 0 =
Disable; 1 = Enable 2
5 0 Reserved
4 0 Reserved
3 45
0 FS2
2 48
0 FS1
11
0 FS0
0 0 Write Enable 3
Notes:
1. Write Disable. A '1' written to this bit after a '1' is written to BYTE0/bit 0 will permanently disable writing to I2C until
the part is powered off. Once the clock generator has been write disabled, the SMBus controller should still accept and
acknowledge subsequent write cycles but it should not modify any of the registers.
2. Spread Pin SS Bit Spread Enable
0 0 Disabled
0 1 Enabled
1 0 Enabled
1 1 Enabled
3. A '1' written to this bit after power-up will enable writing to I2C. Subsequent '0's written to this bit will disable
modification of all registers except this single bit. When a '1' is written to Byte 0 Bit 7, all modification is permanently
disabled until the device power cycles. Block write transactions to the interface will complete, however unless the
interface has been previously unlocked, the writes will have no effect. The effect of writing to this bit does not take effect
until the subsequent block write command.
4. Clarification on frequency select on power-up:
i. Upon power-up, Byte0, bits (5:1) [FS(4:0)] are set to default hardware settings.
ii. A '1' is written to Byte0, bit 0 to enable software control.
iii. Every time Byte0 is written, frequency input defaults will be affected.
iv. If a '0' is written to Byte0, bit0, the software control is disabled. Disabling software control does not cause the
contents of Byte0
to default back to hardware setting for FS(4:0).
0499C—11/01/04
5
5 Page 
ICS950401
Electrical Characteristics - REF
TA = 0 - 70º C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
Output High Voltage
VOH5 IOH = -12 mA
Output Low Voltage
VOL5 IOL = 9 mA
Output High Current
IOH5 VOH = 2.0 V
Output Low Current
Rise Edge Rate1
Fall Edge Rate1
Duty Cycle1
IOL5 VOL = 0.8 V
Measured from 20-80%
Measured from 80-20%
dt5 VT = 50%
Jitter, Cycle-to-cycle1 tjcyc-cyc2B Mesured on rising edge @ 1.5V
Jitter, Accumulated1
1Guaranteed by design, not 100% tested in production.
MIN
2.4
16
0.5
0.5
45
TYP MAX UNITS
V
0.4 V
-22 mA
mA
2 V/ns
2 V/ns
55 %
0 1000 ps
-1000
1000 ps
Electrical Characteristics - 24MHz, 48MHz
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
Output High Voltage
VOH5 IOH = -12 mA
2.4
Output Low Voltage
VOL5 IOL = 9 mA
Output High Current
IOH5
VOH = 2.0 V
Output Low Current
Rise Edge Rate1
Fall Edge Rate1
Duty Cycle1
Jitter, Absolute1
IOL5
dt5
tjabs5
VOL = 0.8 V
Measured from 20-80%
Measured from 80-20%
VT = 50%
VT = 1.5 V
16
0.5
0.5
45
-1
TYP
Jitter, Cycle-to-cycle1 tjcyc-cyc2B VT = VX, for 24_48MHz clock
0
MAX UNITS
V
0.4 V
-22 mA
mA
2 V/ns
2 V/ns
55 %
1 ns
500 ps
Jitter, Cycle-to-cycle1
Output Impedance
tjcyc-cyc2B
ZO
VT = VX, for 48MHz clock
VO = VX
0 200 ps
20 60 Ω
0499C—11/01/04
11
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| PDF Descargar | [ Datasheet ICS950401.PDF ] | |
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