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PDF ICS950405 Data sheet ( Hoja de datos )
| Número de pieza | ICS950405 | |
| Descripción | AMD - K8 System Clock Chip | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
ICS950405
AMD - K8™ System Clock Chip
Recommended Application:
AMD K8 System Clock with AMD, VIA or ALI Chipset
Output Features:
• 2 - Differential pair push-pull CPU clocks @
3.3V
• 9 - PCICLK (Including 1 free running) @ 3.3V
• 3 - Selectable PCICLK/HTTCLK @ 3.3V
• 1 - HTTCLK @ 3.3V
• 1 - 48MHz @ 3.3V fixed.
• 1 - 24/48MHz @ 3.3V
• 3 - REF @ 3.3V, 14.318MHz.
Features:
• Programmable output frequency.
• Programmable output divider ratios.
• Programmable output rise/fall time.
• Programmable output skew.
• Programmable spread percentage for EMI control.
• Watchdog timer technology and RESET# output to
reset system
if system malfunctions.
• Programmable watch dog safe frequency.
• Support I2C Index read/write and block read/write
operations.
• Uses external 14.318MHz crystal.
• Supports Hyper Transport Technology (HTTCLK).
Functionality
FS3 FS2 FS1 FS0
CPU
MHz
HTT
MHz
0 0 0 0 100.90 67.27
0 0 0 1 133.90 66.95
0 0 1 0 168.00 67.20
0 0 1 1 202.00 67.33
0 1 0 0 100.20 66.80
0 1 0 1 133.50 66.75
0 1 1 0 166.70 66.68
0 1 1 1 200.40 66.80
1 0 0 0 150.00 60.00
1 0 0 1 180.00 60.00
1 0 1 0 210.00 70.00
1 0 1 1 240.00 60.00
1 1 0 0 270.00 67.50
1 1 0 1 233.33 66.67
1 1 1 0 266.67 66.67
1 1 1 1 300.00 75.00
PCI
MHz
33.63
33.48
33.60
33.67
33.40
33.38
33.34
33.40
30.00
30.00
35.00
30.00
33.75
33.33
33.33
37.50
Pin Configuration
*FS0/REF0 1
VDDHTT 2
X1 3
X2 4
GND 5
*ModeA/HTTCLK0 6
*ModeB/PCICLK8/HTTCLK1 7
PCICLK9/HTTCLK2 8
VDDPCI 9
GND 10
PCICLK11/HTTCLK3 11
PCICLK10 12
PCICLK0 13
PCICLK1 14
GND 15
VDDPCI 16
PCICLK2 17
PCICLK3 18
VDDPCI 19
GND 20
2XPCICLK4 21
2XPCICLK5 22
2XPCICLK6 23
2XPCICLK7 24
48 REF1/FS1*
47 GND
46 VDDREF
45 REF2/FS2*
44 Reset#
43 VDDA
42 GND
41 CPUCLK8T0
40 CPUCLK8C0
39 GND
38 VDDCPU
37 CPUCLK8T1
36 CPUCLK8C1
35 VDDCPU
34 GND
33 GND
32 PD#*
31 48MHz/FS3**
30 GND
29 AVDD48
28 24_48MHz/Sel24_48#*
27 GND
26 SDATA
25 SCLK
48-SSOP
* Internal Pull-Up Resistor
2X This Output has 2X Default Drive and can be programmaed lower via IIC
0802F—04/22/05
1 page  
ICS950405
General I2C serial interface information
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will acknowledge
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
(see Note 2)
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte
location = N
• ICS clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D3
(H)
• ICS clock will acknowledge
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host)
ICS (Slave/Receiver)
T starT bit
Slave Address D2(H)
WR WRite
ACK
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
ACK
Byte N + X - 1
P stoP bit
ACK
0802F—04/22/05
5
Index Block Read Operation
Controller (Host)
ICS (Slave/Receiver)
T starT bit
Slave Address D2(H)
WR WRite
ACK
Beginning Byte = N
ACK
RT Repeat starT
Slave Address D3(H)
RD ReaD
ACK
ACK
ACK
Data Byte Count = X
Beginning Byte N
N Not acknowledge
P stoP bit
Byte N + X - 1
5 Page 
ICS950405
Electrical Characteristics - K8 Push Pull Differential Pair
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =AMD64 Processor Test Load
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS NOTES
Rising Edge Rate
Falling Edge Rate
Differential Voltage
Change in VDIFF_DC
Magnitude
Common Mode Voltage
δV/δt
δV/δt
VDIFF
∆VDIFF
VCM
Measured at the AMD64 processor's
test load. 0 V +/- 400 mV (differential
2
2
0.4
-150
Measured at the AMD64 processor's
test load. (single-ended measurement) 1.05
10 V/ns
10 V/ns
2.3 V
150 mV
1.45 V
1
1
1
1
1
Change in Common
Mode Voltage
∆VCM
-200
200 mV
1
Jitter, Cycle to cycle
tjcyc-cyc
Measurement from differential
wavefrom. Maximum difference of cycle
time between 2 adjacent cycles.
0
200 ps
1
Measured using the JIT2 software
package with a Tek 7404 scope.
Jitter, Accumulated
tja
TIE (Time Interval Error) measurement
technique:
-1000
1000
Sample resolution = 50 ps,
Duty Cycle
Sample Duration = 10 µs
dt3
Measurement from differential
wavefrom
45
53
Average value during switching
Output Impedance
RON transition. Used for determining series 15
55
termination value.
Group Skew
tsrc-skew
Measurement from differential
wavefrom
250
1Guaranteed by design and characterization, not 100% tested in production.
2 All accumulated jitter specifications are guaranteed assuming that REF is at 14.31818MHz
3 Spread Spectrum is off
%
Ω
ps
1,2,3
1
1
1
0802F—04/22/05
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ICS950405.PDF ] | |
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