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PDF SAA32Mxxx Data sheet ( Hoja de datos )
| Número de pieza | SAA32Mxxx | |
| Descripción | Double Data Rate SDRAM | |
| Fabricantes | SpecTek | |
| Logotipo |  |
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128Mb: x4, x8, x16
DDR SDRAM
DOUBLE DATA RATE
(DDR) SDRAM
Timing – Cycle Time
7.5ns @ CL = 2.5 (PC2100)
10ns @ CL = 2.5 (PC1600)
-75A
-8A
• PC1600 and PC2100 compatible
• VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V
Part number example: SAA16M8T95AV4TL-75A
(For part numbers prior to December
2004, refer to page 13 for decoding.)
• Bi-directional data strobe (DQS) transmitted/ received with
data, i.e., source-synchronous data capture (x16 has two –
one per byte)
• Internal, pipelined double-data-rate (DDR) architecture;
two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-aligned
with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data (x16 has two –
one per byte)
• Programmable burst lengths: 2, 4, or 8
• Auto precharge option
• Auto Refresh
• Longer lead TSOP for improved reliability (OCPL)
• 2.5V I/O (SSTL_2 compatible)
Options:
Family
SpecTek Memory
Configuration
32 Meg x 4 (8 Meg x 4 x 4 banks)
16 Meg x 8 (4 Meg x 8 x 4 banks)
8 Meg x 16 (2 Meg x 16 x 4 banks)
Design ID
DDR 128 Megabit Design
(Call SpecTek Sales for details on
availability of “x” placeholders)
Voltage and refresh
2.5V, Auto Refresh
2.5V, Self or Auto Refresh
Plastic Package – OCPL
66-pin TSOP
(400 mil width, 0.65mm pin pitch)
Designation:
SAA
32M4
16M8
8M16
Yx6x
V4
R4
TL
PDF: 09005aef80505d1b / Source: 09005aef80469e44
128Mb: x4, x8, x16 DDR SDRAM
Rev: 11/23/2004
1
www.spectek.com
SpecTek reserves the right to change products or specifications
without notice. © 2001, 2002, 2004 SpecTek
1 page  
CAPACITANCE (x4, x8)
(25°C < TA < +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V)
PARAMETER
SYMBOL
Delta Input/Output Capacitance: DQs, DQS, DM
Delta Input Capacitance: Command and Address
Delta Input Capacitance: CK, CK#
Delta Input Capacitance: DQs, DQS, DM
Input Capacitance: Command and Address
Input Capacitance: CK, CK#
Input Capacitance: CKE
DCIO
DCI1
DCI2
CIO
CI1
CI2
CI3
MIN
--
--
--
4.0
2.0
2.0
2.0
128Mb: x4, x8, x16
DDR SDRAM
MAX
0.50
0.50
0.25
5.0
3.0
3.0
3.0
UNITS
pF
pF
pF
pF
pF
pF
pF
NOTES
24
29
29
IDD SPECIFICATIONS AND CONDITIONS (x4, x8)
(25°C < TA < +70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V)
PARAMETER/CONDITION
SYMBOL -75 -8 UNITS NOTES
OPERATING CURRENT: One bank; Active-Precharge; tRC = tRC (MIN);
tCK = tCK (MIN); DQ, DM, and DQS inputs changing once per clock
IDD0
105 100 mA 22, 48
cycle; Address and control inputs changing once every two clock cycles;
OPERATING CURRENT: One bank; Active-Read-Precharge; Burst = 2;
tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control
IDD1
120 115 mA 22, 48
inputs changing once per clock cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle;
Power-down mode; tCK = tCK(MIN); CKE=LOW;
IDD2P
10 10
mA 23, 32,
50
IDLE STANDBY CURRENNT: CS# = HIGH; All banks idle; tCK = tCK
IDD2N
50 45
mA
51
(MIN); CKE = HIGH; Address and other control inputs changing once per
clock cycle. VIN = VREF for DQ, DQS, and DM
ACTIVE POWER-DOWN STANDBY CURRENT: One bank active;
Power-down mode; tCK = tCK (MIN); CKE = LOW
IDD3P
18 18
mA 23, 32,
50
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One bank;
Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and
IDD3N
50 45
mA
22
DQS inputs changing twice per clock cycle; Address and other control
inputs changing once per clock cycle.
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank
active; Address and control inputs changing once per clock cycle; tCK =
IDD4R
120 110
mA
22, 48
tCK (MIN); IOUT = 0mA
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank
active; Address and control inputs changing once per clock cycle; tCK =
tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle
IDD4W
120 110
mA
22
AUTO REFRESH CURRENT
tRC = tRFC (MIN)
IDD5
250 225 mA 22, 50
SELF REFRESH CURRENT (Part number ‘R’ only)
IDD7
22
mA
11
OPERATING CURRENT: Four bank interleaving READs (BL = 4) with
auto precharge, tRC = tRC (MIN); tCK = tRC (MIN); Address and control
IDD8
330 285 mA 22, 49
inputs change only during Active, READ, or WRITE commands.
PDF: 09005aef80505d1b / Source: 09005aef80469e44
128Mb: x4, x8, x16 DDR SDRAM
Rev: 11/23/2004
5
www.spectek.com
SpecTek reserves the right to change products or specifications
without notice. © 2001, 2002, 2004 SpecTek
5 Page 
128Mb: x4, x8, x16
DDR SDRAM
NOTES, continued
REFRESH command is registered, CKE must be active at each
45. Note 45 is not used.
rising clock edge, until tREF later.
46. tRAP > tRCD.
51. IDD2N specifies the DQ, DQS, and DM to be
47. Note 47 is not used.
driven to a valid high or low logic level. IDD2Q is
48. Random addressing changing 50% of data
similar to IDD2F except IDD2Q specifies the
changing at every transfer.
address and control inputs to remain stable.
49. Random addressing changing 100% of data
Although IDD2F, IDD2N, and IDD2Q are similar,
changing at every transfer.
IDD2F is “worst case.”
50. CKE must be active (high) during the entire time a refr5e2sh. Whenever the operating frequency is altered, not
command is executed. That is, from the time the AUTO including jitter, the DLL is required to be reset.
This is followed by 200 clock cycles.
PDF: 09005aef80505d1b / Source: 09005aef80469e44
128Mb: x4, x8, x16 DDR SDRAM
Rev: 11/23/2004
11
www.spectek.com
SpecTek reserves the right to change products or
specifications without notice. © 2001, 2002, 2004 SpecTek
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet SAA32Mxxx.PDF ] | |
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