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PDF DS1646 Data sheet ( Hoja de datos )
| Número de pieza | DS1646 | |
| Descripción | Nonvolatile Timekeeping RAM | |
| Fabricantes | Dallas Semiconducotr | |
| Logotipo |  |
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DS1646/DS1646P
Nonvolatile Timekeeping RAM
www.dalsemi.com
FEATURES
Integrates NV SRAM, real time clock,
crystal, power-fail control circuit and lithium
energy source
Clock registers are accessed identically to the
static RAM. These registers are resident in
the eight top RAM locations
Totally nonvolatile with over 10 years of
operation in the absence of power
BCD coded year, month, date, day, hours,
minutes, and seconds with leap year
compensation valid up to 2100
Power-fail write protection allows for ±10%
VCC power supply tolerance
DS1646 only (DIP Module)
− Standard JEDEC bytewide 128k x 8 RAM
pinout
DS1646P only (PowerCap® Module Board)
− Surface mountable package for direct
connection to PowerCap containing battery
and crystal
− Replaceable battery (PowerCap)
− Power-fail output
− Pin-for-pin compatible with other densities
of DS164XP Timekeeping RAM
ORDERING INFORMATION
DS1646
32-pin DIP module
*DS1646P
34-pin PowerCap Module
Board
PIN ASSIGNMENT
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 VCC
31 A15
30 NC
29 WE
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE
21 DQ7
20 DQ6
19 DQ5
18 DQ4
17 DQ3
32-Pin Encapsulated Package
NC
A15
A16
PFO
VCC
WE
OE
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
X1
GND VBAT
X2
17
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
34-Pin PowerCap Module Board
(Uses DS9034PCX PowerCap)
NC
NC
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
*DS9034PCX
Power Cap
(Required; must be ordered
separately)
1 of 11
022101
1 page  
WRITING DATA TO RAM OR CLOCK
DS1646/DS1646P
The DS1646 is in the write mode whenever WE and CE are in their active state. The start of a write is
referenced to the latter occurring high to low transition of WE and CE . The addresses must be held valid
throughout the cycle. CE or WE must return inactive for a minimum of tWR prior to the initiation of
another read or write cycle. Data in must be valid tDS prior to the end of write and remain valid for tDH
afterward. In a typical application, the OE signal will be high during a write cycle. However, OE can be
active provided that care is taken with the data bus to avoid bus contention. If OE is low prior to WE
transitioning low the data bus can become active with read data defined by the address inputs. A low
transition on WE will then disable the outputs tWEZ after WE goes active.
DATA RETENTION MODE
When VCC is within nominal limits (VCC > 4.5 volts) the DS1646 can be accessed as described above with
read or write cycles. However, when VCC is below the power-fail point VPF (point at which write
protection occurs) the internal clock registers and RAM are blocked from access. This is accomplished
internally by inhibiting access via the CE signal. At this time the power-fail output signal ( PFO ) will be
driven active low and will remain active until VCC returns to nominal levels. When VCC falls below the
level of the internal battery supply, power input is switched from the VCC pin to the internal battery and
clock activity, RAM, and clock data are maintained from the battery until VCC is returned to nominal
level.
5 of 11
5 Page 
DS1646P WITH DS9034PCX ATTACHED
DS1646/DS1646P
PKG
DIM
A
B
C
D
E
F
G
MIN
0.920
0.955
0.240
0.052
0.048
0.015
0.020
INCHES
NOM
0.925
0.960
0.245
0.055
0.050
0.020
0.025
MAX
0.930
0.965
0.250
0.058
0.052
0.025
0.030
RECOMMENDED POWERCAP MODULE LAND PATTERN
PKG
DIM
A
B
C
D
E
INCHES
MIN
NOM
MAX
- 1.050 -
- 0.826 -
- 0.050 -
- 0.030 -
- 0.112 -
11 of 11
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet DS1646.PDF ] | |
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