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PDF K9K8G08U0M Data sheet ( Hoja de datos )
| Número de pieza | K9K8G08U0M | |
| Descripción | 1G x 8 Bit / 2G x 8 Bit NAND Flash Memory | |
| Fabricantes | Samsung semiconductor | |
| Logotipo |  |
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K9K8G08U1M
K9F4G08U0M
Document Title
512M x 8 Bits / 1G x 8 Bits NAND Flash Memory
Revision History
Revision No History
0.0 1. Initial issue
Advance
FLASH MEMORY
Draft Date Remark
Nov. 15. 2004 Advance
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The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near your office.
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K9K8G08U1M
K9F4G08U0M
K9K8G08U1M-ICB0/IIB0
A B C DE FG HJ K L M N
NC NC
NC
NC NC NC
7
NC
/RE1
R/B2
IO7-2 IO6-2
IO5-2
NC
6
Vcc /RE2 Vss
IO7-1 IO5-1
Vcc
5
4
/CE1 /CE2
R/B1 /WP2 IO6-1
IO4-1 IO4-2
3
CLE1 CLE2 /WE1
IO0-1 IO2-1
Vss
IO3-2
2
Vss ALE2 /WP1 IO1-1 IO3-1 Vss
1
NC
ALE1 /WE2
IO0-2 IO1-2
IO2-2
NC
NC NC NC
NC NC NC
Advance
FLASH MEMORY
et4U.com
PACKAGE DIMENSIONS
52-ULGA (measured in millimeters)
Top View
12.00±0.10
#A1
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Bottom View
DataSheet4U.com2.00
7
12.00±0.10
1.00 10.00 1.00
6 54 3 2
1
(Datum A)
1.00
1.00
(Datum B)
A
B
C
D
E
F
G
H
J
K
L
M
N
A
B
0.10 C
12-∅1.00±0.05
∅0.1 M C AB
Side View
17.00±0.10
41-∅0.70±0.05
∅0.1 M C AB
5
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K9K8G08U1M
K9F4G08U0M
Advance
FLASH MEMORY
Program / Erase Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
Program Time
tPROG(2)
-
200 700
µs
Dummy Busy Time for Two-Plane Page Program
tDBSY
-
0.5
1
µs
Number of Partial Program Cycles
in the Same Page
Main Array
Spare Array
Nop
-
-
-
-
4 cycles
4 cycles
Block Erase Time
tBERS
-
1.5 2
ms
NOTE : 1. Typical value is measured at Vcc=3.3V, TA=25°C. Not 100% tested.
2. Typical program time is defined as the time that more than 50% of the whole pages are programmed at Vcc of 3.3V and temperature of 25°C
within.
AC Timing Characteristics for Command / Address / Data Input
Parameter
CLE Setup Time
CLE Hold Time
CE Setup Time
CE Hold Time
WE Pulse Width
ALE Setup Time
ALE Hold Time
S h e e t 4 UD.atacSoetump Time
Data Hold Time
Write Cycle Time
WE High Hold Time
ALE to Data Loading Time
Symbol
Min
Max
tCLS(1)
12
-
tCLH
5
-
tCS(1)
20
-
tCH 5
-
tWP 12
-
tALS(1)
12
-
tALH
5
-
tDS(1)
12
-
tDH 5
-
D tWaC t a S h e e25t 4 U . c o m-
tWH 10
-
tADL(2)
70
-
NOTES : 1. The transition of the corresponding control pins must occur only once while WE is held low
2. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet K9K8G08U0M.PDF ] | |
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