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PDF PALCE610 Data sheet ( Hoja de datos )

Número de pieza PALCE610
Descripción (PALCE610 / PALCE600) EE CMOS High Performance Programmable Array Logic
Fabricantes ETC 
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No Preview Available ! PALCE610 Hoja de datos, Descripción, Manual

USE GAL DEVICES FOR NEW DESIGNS
FINAL
COM’L: H-15/25
PALCE610 Family
Lattice Semiconductor
EE CMOS High Performance Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
s Lattice/Vantis Programmable Array Logic (PAL)
architecture
s Electrically-erasable CMOS technology
providing half power (90 mA ICC) at high speed
— -15 = 15-ns tPD
— -25 = 25-ns tPD
s Sixteen macrocells with configurable I/O
architecture
s Registered or combinatorial operation
s Registers programmable as D, T, J-K, or S-R
s Asynchronous clocking via product term or
bank register clocking from external pins
s Register preload for testability
s Power-up reset for initialization
s Space-saving 24-pin SKINNYDIP and 28-pin
PLCC packages
s Fully tested for 100% programming yield and
high reliability
s Extensive third-party software and programmer
support through FusionPLD partners
GENERAL DESCRIPTION
The PALCE610 is a general purpose PAL device and is
functionally and fuse map equivalent to the EP610. It
can accommodate logic functions with up to 20 inputs
and 16 outputs. There are 16 I/O macrocells that can be
individually configured to the user’s specifications. The
macrocells can be configured as either registered or
combinatorial. The registers can be configured as D, T,
J-K, or S-R flip-flops.
The PALCE610 uses the familiar sum-of-products logic
with programmable-AND and fixed-OR structure. Eight
product terms are brought to each macrocell to provide
logic implementations.
The PALCE610 is manufactured using advanced
CMOS EE technology providing low power consump-
tion. Moreover, it is a high-speed device having a worst-
case tPD of 15 ns. Space-saving 24-pin SKINNYDIP and
28-pin PLCC packages are offered.
This device can be quickly erased and reprogrammed
providing for easy prototyping. Once a device is pro-
grammed the security bit can be used to provide protec-
tion from copying a proprietary design.
BLOCK DIAGRAM
I I/O16 I/O15
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9 CLK1
4
28 28 28 28 28 28 28 28
Programmable AND Array
40 x 160
28 28 28 28 28 28 28 28
CLK2
2-374
I/O8
I/O7
I/O6
I/O5 I/O4
I/O3
I/O2 I/O1 12950G-1
Publication# 12950 Rev. G Amendment /0
Issue Date: February 1996
CONNECTION DIAGRAMS
Top View
SKINNYDIP
CLK1
I
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
I
GND
1
2
3
4
5
6
7
8
9
10
11
12
24 VCC
23 I
22 I/O1
21 I/O2
20 I/O3
19 I/O4
18 I/O5
17 I/O6
16 I/O7
15 I/O8
14 I
13 CLK2
12950G-2
Note:
Pin 1 is marked for orientation
PIN DESIGNATIONS
CLK = Clock
GND = Ground
I = Input
I/O = Input/Output
NC = No Connect
VCC = Supply Voltage
PLCC/LCC
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
NC
4 3 2 1 28 27 26
5 25
6 24
7 23
8 22
9 21
10 20
11 19
12 13 14 15 16 17 18
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
NC
12950G-3
PALCE610 Family
2-375

1 page




PALCE610 pdf
CAPACITANCE (Note 1)
Parameter
Symbol
CIN
Parameter Description
Input Capacitance
COUT
Output Capacitance
Test Conditions
VIN = 2.0 V
VOUT = 2.0 V
VCC = 5.0 V
TA = +25°C
f = 1 MHz
Typ Unit
8
pF
8
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
Parameter
Symbol
tPD
Parameter Description
Input or Feedback to Combinatorial Output
-15
Min Max
15
-25
Min Max
25
Unit
ns
tS Setup Time from Input or Feedback to Clock
12 15 ns
tH Hold Time
0 0 ns
tCO Clock to Output
8 12 ns
tWL Clock
tWH Width
LOW
HIGH
6 10 ns
6 10 ns
Maximum
External Feedback 1/(tS + tCO)
50
37 MHz
fMAX
Frequency
Internal Feedback 1/(tS + tCF)
76.1
40
MHz
(Note 3)
(fCNT)
(Note 5)
No Feedback
1/(tWH + tWL)
83.3
50
MHz
tEA Input to Output Enable Using Product Term Control
15 25 ns
tER Input to Output Disable Using Product Term Control
15 25 ns
tAR Asynchronous Reset to Registered Output
15 25 ns
tARW Asynchronous Reset Width
10 15 ns
tARR Asynchronous Reset Recovery Time
15 25 ns
tSA Setup Time from Input or Feedback to Clock (Note 4)
5
8
ns
tHA Hold Time (Note 4)
5 12 ns
tCOA Clock to Output (Note 4)
15 27 ns
tWLA
tWHA
fMAXA
Clock
Width
Maximum
Frequency
(Notes 3
and 4)
LOW (Note 4)
HIGH (Note 4)
External Feedback
1/(tSA + tCOA)
Internal Feedback (fCNT)
No Feedback
1/(tWLA + tWHA)
6
6
50
61.6
83.3
10
10
28.6
29.4
50
ns
ns
MHz
MHz
MHz
Notes:
2. See Switching Test Circuit for test conditions.
3. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where frequency may be affected.
4. These parameters are measured using the asynchronous product-term clock.
5. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation:
tCF = 1/fMAX (internal feedback) – tS.
2-382
PALCE610H-15/25 (Com’l)
SWITCHING WAVEFORMS
Input or
Feedback
Combinatorial
Output
VT
tPD
VT
12950G-6
Combinatorial Output
Input or
Feedback
Clock
Registered
Output
VT
tS tH
VT
tCO
Registered Output
VT
12950G-7
Clock
tWH
tWL
Clock Width
VT
12950G-8
Input
Output
VT
tER tEA
VOH - 0.5V
VOL + 0.5V
VT
12950G-9
Input to Output Disable/Enable
Input or
Feedback
Product-Term
Clock
tWHA
tWLA
Clock Width Using
Product-Term Clock
VT
12950G-10
Product-Term
Clock
Registered
Output
Input
Asserting
Asynchronous
Reset
Registered
Output
tARW
VT
tAR
VT
tARR
Clock
VT
Notes:
Asynchronous Reset
1. VT = 1.5 V
2. Input pulse amplitude 0 V to 3.0 V
3. Input rise and fall times 2 ns–5 ns typical.
12950G-12
PALCE610 Family
VT
tSA tHA
VT
tCOA
VT
12950G-11
Registered Output Using
Product-Term Clock
2-383

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