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PDF EPC8xxx Data sheet ( Hoja de datos )

Número de pieza EPC8xxx
Descripción (EPC4 / EPC8 / EPC16) Enhanced Configuration Devices
Fabricantes Altera 
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CF52002-2.1
Features
2. Enhanced Configuration
Devices (EPC4, EPC8 &
EPC16) Data Sheet
Enhanced configuration devices include EPC4, EPC8, and EPC16
devices
Single-chip configuration solution for Stratix® series, Cyclone™
series, APEX™ II, APEX 20K (including APEX 20K, APEX 20KC, and
APEX 20KE), Mercury™, ACEX® 1K, and FLEX® 10K (FLEX 10KE
and FLEX 10KA) devices
Contains 4-, 8-, and 16-Mbit flash memories for configuration data
storage
On-chip decompression feature almost doubles the effective
configuration density
Standard flash die and a controller die combined into single stacked
chip package
External flash interface supports parallel programming of flash and
external processor access to unused portions of memory
Flash memory block/sector protection capability via external
flash interface
Supported in EPC16 and EPC4 devices
Page mode support for remote and local reconfiguration with up to
eight configurations for the entire system
Compatible with Stratix series Remote System Configuration
feature
Supports byte-wide configuration mode fast passive parallel (FPP);
8-bit data output per DCLK cycle
Supports true n-bit concurrent configuration (n = 1, 2, 4, and 8) of
Altera FPGAs
Pin-selectable 2-ms or 100-ms power-on reset (POR) time
Configuration clock supports programmable input source and
frequency synthesis
Multiple configuration clock sources supported (internal
oscillator and external clock input pin)
External clock source with frequencies up to 133 MHz
Internal oscillator defaults to 10 MHz; Programmable for higher
frequencies of 33, 50, and 66 MHz
Clock synthesis supported via user programmable divide
counter
Available in the 100-pin plastic quad flat pack (PQFP) and the 88-pin
Ultra FineLine BGA® packages
Vertical migration between all devices supported in the 100-pin
PQFP package
Supply voltage of 3.3 V (core and I/O)
Altera Corporation
August 2005
2–1

1 page




EPC8xxx pdf
Altera Corporation
August 2005
Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet
In addition to transmitting configuration data to the FPGAs, the
configuration circuit is also responsible for pausing configuration
whenever there is insufficient data available for transmission. This occurs
when the flash read bandwidth is lower than the configuration write
bandwidth. Configuration is paused by stopping the DCLK to the FPGA,
when waiting for data to be read from the flash or for data to be
decompressed. This technique is called “Pausing DCLK.”
The enhanced configuration device flash memories feature a 90-ns access
time (approximately 10 MHz). Hence, the flash read bandwidth is limited
to about 160 megabits per second (Mbps) (16-bit flash data bus, DQ[], at
10 MHz). However, the configuration speeds supported by Altera FPGAs
are much higher and translate to high configuration write bandwidths.
For instance, 100-MHz Stratix FPP configuration requires data at the rate
of 800 Mbps (8-bit DATA[] bus at 100 MHz). This is much higher than the
160 Mbps the flash memory can support, and is the limiting factor for
configuration time. Compression increases the effective flash read
bandwidth since the same amount of configuration data takes up less
space in the flash memory after compression. Since Stratix configuration
data compression ratios are approximately two, the effective read
bandwidth doubles to about 320 Mbps.
Finally, the configuration controller also manages errors during
configuration. A CONF_DONE error occurs when the FPGA does not de-
assert its CONF_DONE signal within 64 DCLK cycles after the last bit of
configuration data is transmitted. When a CONF_DONE error is detected,
the controller pulses the OE line low, which pulls nSTATUS low and
triggers another configuration cycle.
A cyclic redundancy check (CRC) error occurs when the FPGA detects
corruption in the configuration data. This corruption could be a result of
noise coupling on the board such as poor signal integrity on the
configuration signals. When this error is signaled by the FPGA (by
driving the nSTATUS line low), the controller stops configuration. If the
Auto-Restart Configuration After Error option is enabled in the FPGA,
it releases its nSTATUS signal after a reset time-out period and the
controller attempts to reconfigure the FPGA.
After the FPGA configuration process is complete, the controller drives
DCLK low and the DATA[] pins high. Additionally, the controller tri-
states its internal interface to the flash memory, enables the weak internal
pull-ups on the flash address and control lines, and enables bus-keep
circuits on flash data lines.
The following sections briefly describe the different configuration
schemes supported by the enhanced configuration device: FPP, PS, and
concurrent configuration.
2–5
Configuration Handbook, Volume 2

5 Page





EPC8xxx arduino
Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet
Figure 2–3. Concurrent Configuration of Multiple FPGAs in PS Mode (n = 8)
n
(6)
N.C.
n
(6)
N.C.
n
(6)
N.C.
VCC (1) VCC (1)
MSEL
nCEO
FPGA0
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
nCE
MSEL
nCEO
FPGA1
GND
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
nCE
GND
(3)
(3)
MSEL
nCEO
FPGA7
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
nCE
GND
Enhanced Configuration
Device
WE#C
RP#C
DCLK
DATA0
DATA1
OE (3)
nCS (3)
WE#F
RP#F
A[20..0]
RY/BY#
CE#
OE#
DQ[15..0]
nINIT_CONF (2)
DATA 7
(1)
VCC
WP#
BYTE# (5)
TM1
VCCW
PORSEL
PGM[2..0]
EXCLK
VCC (1)
(4)
(4)
(4)
TMO
GND
C-A0 (5)
C-A1 (5)
C-A15 (5)
C-A16 (5)
A0-F
A1-F
A15-F
A16-F
N.C.
N.C.
N.C.
N.C.
N.C.
Notes to Figure 2–3:
(1) Connect VCC to the same supply voltage as the configuration device.
(2) The nINIT_CONF pin is available on enhanced configuration devices and has an internal pull-up resistor that is
always active. This means an external pull-up resistor is not required on the nINIT_CONF/nCONFIG line. The
nINIT_CONF pin does not need to be connected if its functionality is not used. If nINIT_CONF is not used, nCONFIG
must be pulled to VCC either directly or through a resistor.
(3) The enhanced configuration devices’ OE and nCS pins have internal programmable pull-up resistors. If internal
pull-up resistors are used, external pull-up resistors should not be used on these pins. The internal pull-up resistors
are used by default in the Quartus II software. To turn off the internal pull-up resistors, check the Disable nCS and
OE pull-ups on configuration device option when generating programming files.
(4) For PORSEL, PGM[], and EXCLK pin connections, refer to Table 2–9.
(5) In the 100-pin PQFP package, you must externally connect the following pins: C-A0 to F-A0, C-A1 to F-A1, C-A15
to F-A15, C-A16 to F-A16, and BYTE# to VCC. Additionally, you must make the following pin connections in both
100-pin PQFP and 88-pin Ultra FineLine BGA packages: C-RP# to F-RP#, C-WE# to F-WE#, TM1 to VCC, TM0 to
GND, and WP# to VCC.
(6) Connect the FPGA MSEL[] input pins to select the PS configuration mode. For details, refer to the appropriate
FPGA family chapter in the Configuration Handbook.
Altera Corporation
August 2005
2–11
Configuration Handbook, Volume 2

11 Page







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