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PDF CEF04N6 Datasheet ( Hoja de datos )

Número de pieza CEF04N6
Descripción N-Channel Logic Level Enhancement Mode Field Effect Transistor
Fabricantes Chino-Excel Technology 
Logotipo Chino-Excel Technology Logotipo

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CEF04N6 Hoja de datos, Descripción, Manual
CEF04N6
Feb. 2003
N-Channel Logic Level Enhancement Mode Field Effect Transistor
FEATURES
600V , 2.5A , RDS(ON)=2.5@VGS=10V.
6 Super high dense cell design for extremely low RDS(ON).
High power and current handling capability.
TO-220F full-pak for through hole
G
D
G
D
S
TO-220F
S
ABSOLUTE MAXIMUM RATINGS (Tc=25 C unless otherwise noted)
Parameter
Symbol
Drain-Source Voltage
VDS
Gate-Source Voltage
VGS
Drain Current-Continuous
-Pulsed
ID
IDM
Drain-Source Diode Forward Current
IS
Maximum Power Dissipation @Tc=25 C
Derate above 25 C
Operating and Storage Temperautre Range
PD
TJ, TSTG
Limit
600
Ć30
2.5
10
2.5
35
0.28
-55 to 150
Unit
V
V
A
A
A
W
W/ C
C
THERMAL CHARACTERISTICS
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient
RįJC
RįJA
6-122
3.6
65
C/W
C/W

1 page

CEF04N6 pdf
CEF04N6
15
VDS=480V
12 ID=4A
9
6
3
60
0 10 20 30 40
Qg, Total Gate Charge (nC)
Figure 9. Gate Charge
VDD
RL
VIN
D VOUT
VGS
RGEN G
S
Figure 11. Switching Test Circuit
101
100
RDS(ON) Limit
1ms
100ij
s
-1 TC=25 C
10 Tj=150 C
Single Pulse
100 101 102 103
VDS, Drain-Source Voltage (V)
Figure 10. Maximum Safe
Operating Area
td(on)
VOUT
t on
tr
td(off)
90%
10% INVERTED
toff
tf
90%
10%
VIN
10%
50%
90%
50%
PULSE WIDTH
Figure 12. Switching Waveforms
100
D=0.5
0.2
10-1
0.1
0.05
0.02
0.01
10-2
10-5
Single Pulse
10-4 10-3 10-2 10-1
Square Wave Pulse Duration (sec)
PDM
t1
t2
1. RįJC (t)=r (t) * RįJC
2. RįJC=See Datasheet
3. TJM-TC = P* RįJC (t)
4. Duty Cycle, D=t1/t2
100
Figure 13. Normalized Thermal Transient Impedance Curve
101
6-126

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