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PDF C9531 Data sheet ( Hoja de datos )

Número de pieza C9531
Descripción PCIX I/O System Clock Generator with EMI Control Features
Fabricantes Cypress Semiconductor 
Logotipo Cypress Semiconductor Logotipo



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C9531
PCIX I/O System Clock Generator with EMI Control Features
Features
• Dedicated clock buffer power pins for reduced noise,
crosstalk and jitter
• Input clock frequency of 25 MHz to 33 MHz
• Output frequencies of XINx1, XINx2, XINx3 and XINx4
• One output bank of 5 clocks.
• One REF XIN clock output.
• SMBus clock control interface for individual clock
disabling and SSCG control
• Output clock duty cycle is 50% (± 5%)
• < 250 ps skew between output clocks within a bank
• Output jitter <175 ps
• Spread Spectrum feature for reduced electromagnetic
interference (EMI)
• OE pin for entire output bank enable control and
testability
• 28-pin SSOP and TSSOP packages
Block Diagram
Table 1. Test Mode Logic Table[1]
OE
HIGH
HIGH
HIGH
HIGH
LOW
Input Pins
S1
LOW
LOW
HIGH
HIGH
X
S0
LOW
HIGH
LOW
HIGH
X
Output Pins
CLK
REF
XIN XIN
2 * XIN
XIN
3 * XIN
XIN
4 * XIN
XIN
Three-state Three-state
Pin Configuration
SSCG#
SSCG
Logic
XIN
XOUT
/N 1
0
SDATA
SCLK
IA(0:2)
S(0,1)
I2C
Control
Logic
CLK0
CLK1
CLK2
CLK3
CLK4
OE
GOOD#
REF
Note:
1. XIN is the frequency of the clock on the device’s XIN pin.
REF
VDD
XIN
XOUT
VSS
S0
S1
GOOD#
VSS
IA0
IA1
IA2
VDDA
OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 SDATA
27 SCLK
26 VSS
25 VDDP
24 CLK0
23 CLK1
22 CLK2
21 VSS
20 VDDP
19 CLK3
18 CLK4
17 VDDA
16 VSS
15 SSCG#
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07034 Rev. *D
Revised May 12, 2003

1 page




C9531 pdf
C9531
Output Clock Three-state Control
All of the clocks in the Bank may be placed in a three-state
condition by bringing their relevant OE pins to a logic low state.
This transition to and from a three-state and active condition
is a totally asynchronous event and clock glitching may occur
during the transitioning states. This function is intended as a
board level testing feature. When output clocks are being
enabled and disabled in active environments the SMBus
control register bits are the preferred mechanism to control
these signals in an orderly and predictable manner.
The output enable pin contains an internal pull-up resistor that
will insure that a logic 1 is maintained and sensed by the
device if no external circuitry is connected to this pin.
Output Clock Frequency Control
control signals is determined by the SMBus register Byte 0 bit
0. At initial power up this bit is set of a logic 1 state and thus
the frequency selections are controlled by the logic levels
present on the device’s S(0,1) pins. If the application does not
use an SMBus interface then hardware frequency selection
S(0,1) must be used. If it is desired to control the output clocks
using an SMBus interface, then this bit (B0b0) must first be set
to a low state. After this is done the device will use the contents
of the internal SMBus register Bytes 0 bits 3 and 4 to control
the output clock’s frequency.
The following formula and schematic may be used to under-
stand and calculate either the loading specification of a crystal
for a design or the additional discrete load capacitance that
must be used to provide the correct load to a known load rated
crystal.
All of the output clocks have their frequency selected by the
logic state of the S0 and S1 control bits. The source of these
CL =
(CXINPCB + CXINFTG + CXINDISC) x (CXOUTPCB) + CXOUTFTG) + CXOUTDISC)
(CXINPCB + CXINFTG + CXINDISC) + (CXOUTPCB) + CXOUTFTG) + CXOUTDISC)
where:
CXTAL = The load rating of the crystal.
CXINFTG = The clock generators XIN pin effective device internal capacitance to ground.
CXOUTFTG = The clock generators XOUT pin effective device internal capacitance to ground.
CXINPCB = The effective capacitance to ground of the crystal to device PCB trace.
CXOUTPCB = The effective capacitance to ground of the crystal to device PCB trace.
CXINDISC = Any discrete capacitance that is placed between the XIn pin and ground.
CXOUTDISC = Any discrete capacitance that is placed between the XIn pin and ground.
CXINPCB
CXOUTPCB
CXINDISC
XIN
CXINFTG
CXOUTDISC
XOUT CXOUTFTG
Clock Generator
As an example and using this formula for this data sheet’s
device, a design that has no discrete loading capacitors
(CDISC) and each of the crystal device PCB traces has a
capacitance (CPCB) to ground of 4 pF (typical value) would
calculate as:
CL =
(4 pF + 36 pF + 0 pF) x (4 pF + 36 pF + 0 pF)
(4 pF + 36 pF + 0 pF) x (4 pF + 36 pF + 0 pF)
= 40 x 40
40 x 40
=
1600
80
= 20 pF.
Therefore, to obtain output frequencies that are as close to this
data sheets specified values as possible, in this design
example, you should specify a parallel cut crystal that is
designed to work into a load of 20 pF.
Document #: 38-07034 Rev. *D
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