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PDF ID82C52 Data sheet ( Hoja de datos )

Número de pieza ID82C52
Descripción CMOS Serial Controller Interface
Fabricantes Intersil Corporation 
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82C52
March 1997
CMOS Serial Controller Interface
Features
• Single Chip UART/BRG
• DC to 16MHz (1M Baud) Operation
• Crystal or External Clock Input
• On-Chip Baud Rate Generator - 72 Selectable Baud
Rates
• Interrupt Mode with Mask Capability
• Microprocessor Bus Oriented Interface
• 80C86 Compatible
• Single +5V Power Supply
• Low Power Operation . . . . . . . . . . . . . . . 1mA/MHz Typ
• Modem Interface
• Line Break Generation and Detection
• Operating Temperature Range:
- C82C52 . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to +70oC
- I82C52 . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
- M82C52 . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
Description
The Intersil 82C52 is a high performance programmable
Universal Asynchronous Receiver/Transmitter (UART) and
Baud Rate Generator (BRG) on a single chip. Utilizing the
Intersil advanced Scaled SAJI IV CMOS process, the 82C52
will support data rates up to 1M baud asynchronously with a
16X clock (16MHz clock frequency).
The on-chip Baud Rate Generator can be programmed for
any one of 72 different baud rates using a single industry
standard crystal or external frequency source. A unique pre-
scale divide circuit has been designed to provide standard
RS-232-C baud rates when using any one of three industry
standard crystals (1.8432MHz, 2.4576MHz, or 3.072MHz).
A programmable buffered clock output (CO) is available and
can be programmed to provide either a buffered oscillator or
16X baud rate clock for general purpose system usage.
Ordering Information
PACKAGE
PDIP
PLCC
CERDIP
SMD#
CLCC
SMD#
TEMPERATURE
RANGE
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
-55oC to +125oC
-55oC to +125oC
1M BAUD
CP82C52
IP82C52
CS82C52
IS82C52
CD82C52
ID82C52
MD82C52/B
8501501XA
MR82C52/B
85015013A
PKG. NO.
E28.6
E28.6
N28.45
N28.45
F28.6
F28.6
F28.6
F28.6
J28.A
J28.A
Pinouts
82C52 (PDIP, CERDIP)
TOP VIEW
RD 1
WR 2
D0 3
D1 4
D2 5
D3 6
D4 7
D5 8
D6 9
D7 10
A0 11
A1 12
IX 13
OX 14
28 CSO
27 VCC
26 DR
25 SDI
24 INTR
23 RST
22 TBRE
21 CO
20 RTS
19 DTR
18 DSR
17 CTS
16 GND
15 SDO
82C52 (PLCC, CLCC)
TOP VIEW
4 3 2 1 28 27 26
D2 5
25 SDI
D3 6
24 INTR
D4 7
23 RST
D5 8
D6 9
22 TBRE
21 CO
D7 10
20 RTS
A0 11
19 DTR
12 13 14 15 16 17 18
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
5-1
File Number 2950.1

1 page




ID82C52 pdf
82C52
Baud Rate Select Register (BRSR)
The 82C52 is designed to operate with a single crystal or
external clock driving the IX input pin. The Baud Rate Select
Register is used to select the divide ratio (one of 72) for the
internal Baud Rate Generator circuitry. The internal circuitry
is separated into two separate counters, a Prescaler and a
Divisor Select. The Prescaler can be set to any one of four
division rates, ÷1, ÷3, ÷4, or ÷5.
The Prescaler design has been optimized to provide
standard baud rates using any one of three popular crystal
frequencies. By using one of these common system clock
frequencies, 1.8432MHz, 2.4576MHz or 3.072MHz and
Prescaler divide ratios of ÷3, ÷4, or ÷5 respectively, the
Prescaler output will provide a constant 614.4KHz. When
this frequency is further divided by the Divisor Select
counter, any of the standard baud rates from 50 Baud to
38.4Kbaud can be selected (see Table 2). Non-standard
baud rates up to 1Mbaud can be selected by using different
input frequencies (crystal or an external frequency input up
to 16MHz) and/or different Prescaler and Divisor Select
ratios.
Regardless of the baud rate, the baud rate generator
provides a clock which is 16 times the desired baud rate. For
example, in order to operate at a 1Mbaud data rate, a
16MHz crystal, a Prescale rate of ÷1, and a Divisor Select
rate of “external” would be used. This would provide a
16MHz clock as the output of the Baud Rate Generator to
the Transmitter and Receiver circuits.
The CO select bit in the BRSR selects whether a buffered
version of the external frequency input (IX input) or the Baud
Rate Generator output (16x baud rate clock) will be output
on the CO output (pin 21). The Baud Rate Generator output
will always be a 50% nominal duty cycle except when “exter-
nal” is selected and the Prescaler is set to ÷3 or ÷5.
D7 D6 D5 D4 D3 D2 D1 D0
Prescaler 00 = ÷ 1
Select 01 = ÷ 3
10 = ÷ 4
11 = ÷ 5
Divisor
Select
00000 = ÷ 2
00001 = ÷ 4
00010 = ÷ 16/3
00011 = ÷ 8
00100 = ÷ 32/3
00101 = ÷ 16
00110 = ÷ 58/3
00111 = ÷ 22
01000 = ÷ 32
01001 = ÷ 64
01010 = ÷ 128
01011 = ÷ 192
01100 = ÷ 256
01101 = ÷ 288
01110 = ÷ 352
01111 = ÷ 512
10000 = ÷ 768
11111 = External (÷ 1)
CO
Select
0 = IX Output
1 = Brg Output (On
Reset, D7 (CO Select)
is Reset to 0)
FIGURE 2. BRSR
TABLE 2.
BAUD RATE
DIVISOR
38.4K
External
19.2K
2
9600
4
7200
16/3
4800
8
3600
32/3
2400
16
2000
58/3
1800
22
1200
32
600 64
300 128
200 192
150 256
134.5
288
110
352
75 512
50 768
NOTE: These baud rates are based upon the following input
frequency/ Prescale divisor combinations.
1.8432MHz and Prescale = ÷ 3
2.4576MHz and Prescale = ÷ 4
3.072MHZ and Prescale = ÷ 5
All baud rates are exact except for:
BAUD RATE
1800
2000
134.5
110
ACTUAL
1745.45
1986.2
133.33
109.09
PERCENT ERROR
3.03%
0.69%
0.87%
0.83%
Modem Control Register
The MCR is a general purpose control register which can be
written to and read from. The RTS and DTR outputs are
directly controlled by their associated bits in this register.
Note that a logic one asserts a true logic level (low) at these
output pins. The Interrupt Enable (INTEN) bit is the overall
control for the INTR output pin. When INTEN is false, INTR
is held false (low).
The Operating Mode bits configure the 82C52 into one of
four possible modes. “Normal” configures the 82C52 for nor-
mal full or half duplex communications. “Transmit Break”'
enables the transmitter to only transmit break characters
(Start, Data and Stop bits all are logic zero). The Echo Mode
causes any data that is received on the SDI input pin to be
retransmitted on the SDO output pin. Note that this output is
a buffered version of the data seen on the SDI input and is
not a resynchronized output. Also note that normal UART
transmission via the Transmitter Register is disabled when
operating in the Echo mode (see Figure 4). The Loop Test
Mode internally routes transmitted data to the receiver
circuitry for the purpose of self test. The transmit data is
5-5

5 Page





ID82C52 arduino
82C52
AC Electrical Specifications VCC = 5.0V ±10%, TA = 0oC to +70oC (C82C52), TA = -40oC to +85oC (l82C52)
TA = -55oC to +125oC (M82C52)
Timing Requirements and Responses
SYMBOL
PARAMETER
MIN
MAX
UNITS
TEST CONDITIONS
(1) TSVCTL Select Setup to Control Leading Edge
30 - ns
(2) TCTHSX Select Hold from Control Trailing Edge
50 - ns
(3) TCTLCTH Control Pulse Width
150 -
ns Control Consists of RD
or WR
(4) TCTHCTL Control Disable to Control Enable
190 -
ns
(5) TRLDV Read Low to Data Valid
- 120 ns 1, See AC Test Circuit
(6) TRHDZ Read Disable
0 60 ns 2, See AC Test Circuit
(7) TDVWH Data Setup Time
50 - ns
(8) TWHDX Data Hold Time
20 - ns
(9) FC Clock Frequency
0 16 MHz TCHCL + TCLCH must
be 62.5ns
(10) TCHCL Clock High Time
25 - ns
(11) TCLCH Clock Low Time
(12) TR/TF IX Input Rise/Fall Time (External Clock)
25 - ns
- tx ns tx 6----F-1---C--- or 50ns
Whichever is smaller
(13) TFCO Clock Output Fall Time
- 15 ns CL = 50pf
(14) TRCO Clock Output Rise Time
- 15 ns CL = 50pf
5-11

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