|
|
PDF UDA1330ATS Data sheet ( Hoja de datos )
| Número de pieza | UDA1330ATS | |
| Descripción | Low-cost stereo filter DAC | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de UDA1330ATS (archivo pdf) en la parte inferior de esta página. Total 24 Páginas | ||
|
No Preview Available !
INTEGRATED CIRCUITS
DATA SHEET
UDA1330ATS
Low-cost stereo filter DAC
Preliminary specification
Supersedes data of 1999 Dec 20
File under Integrated Circuits, IC01
2000 Apr 18
1 page  
Philips Semiconductors
Low-cost stereo filter DAC
Preliminary specification
UDA1330ATS
FUNCTIONAL DESCRIPTION
System clock
The UDA1330ATS operates in slave mode only.
Therefore, in all applications the system devices must
provide the system clock. The system frequency (fsys) is
selectable and depends on the application mode. The
options are: 256fs, 384fs and 512fs for the L3 mode and
256fs or 384fs for the static pin mode. The system clock
must be locked in frequency to the digital interface input
signals.
The UDA1330ATS supports sampling frequencies from
16 to 55 kHz.
Application modes
The application mode can be set with the three-level
pin APPSEL (see Table 1):
• L3 mode
• Static pin mode with fsys = 384fs
• Static pin mode with fsys = 256fs.
Table 1 Selecting application mode and system clock
frequency via pin APPSEL
VOLTAGE ON
PIN APPSEL
VSSD
0.5VDDD
VDDD
MODE
fsys
L3 mode
static pin mode
256fs, 384fs or 512fs
384fs
256fs
In the L3 mode, pin APPL0 must be set to LOW. It should
be noted that when the L3 mode is used, an initialization
must be performed when the IC is powered-up.
Multiple format input interface
DATA FORMATS
The digital interface of the UDA1330ATS supports multiple
format inputs (see Fig.3).
Left and right data-channel words are time multiplexed.
The WS signal must have a 50% duty factor for all
LSB-justified formats.
The BCK clock can be up to 64fs, or in other words the
BCK frequency is 64 times the Word Select (WS)
frequency or less: fBCK ≤ 64 × fWS.
Important: the WS edge MUST fall on the negative edge
of the BCK at all times for proper operation of the digital
interface.
The UDA1330ATS also accepts double speed data for
double speed data monitoring purposes
L3 MODE
This mode supports the following input formats:
• I2S-bus format with data word length of up to 20 bits
• MSB-justified format with data word length up to 20 bits
• LSB-justified format with data word length of
16, 18 or 20 bits.
The function of an application input pin (active HIGH)
depends on the application mode (see Table 2).
Table 2 Functions of application input pins
PIN
APPL0
APPL1
APPL2
APPL3
FUNCTION
L3 MODE STATIC PIN MODE
TEST
L3CLOCK
L3MODE
L3DATA
MUTE
DEEM
SF0
SF1
For example, in the static pin mode the output signal can
be soft muted by setting pin APPL0 to HIGH.
De-emphasis can be switched on for 44.1 kHz by setting
pin APPL1 to HIGH; setting pin APPL1 to LOW will disable
de-emphasis.
STATIC PIN MODE
This mode supports the following input formats:
• I2S-bus format with data word length of up to 20 bits
• LSB-justified format with data word length of
16, 18 or 20 bits.
These four formats are selectable via the static pin codes
SF0 and SF1 (see Table 3).
Table 3 Input format selection using SF0 and SF1
FORMAT
I2S-bus
LSB-justified 16 bits
LSB-justified 18 bits
LSB-justified 20 bits
SF0 SF1
00
01
10
11
2000 Apr 18
5
5 Page 
Philips Semiconductors
Low-cost stereo filter DAC
Preliminary specification
UDA1330ATS
SYSTEM CLOCK FREQUENCY
The system clock frequency is a 2-bit value to select the
external clock frequency.
Table 8 System clock settings
SC1 SC0
0 0 512fs
0 1 384fs
1 0 256fs
1 1 not used
FUNCTION
DATA FORMAT
The data format is a 3-bit value to select the used data
format.
Table 9 Data input format settings
IF2 IF1 IF0
FORMAT
0 0 0 I2S-bus
0 0 1 LSB-justified 16 bits
0 1 0 LSB-justified 18 bits
0 1 1 LSB-justified 20 bits
1 0 0 MSB-justified
1 0 1 not used
1 1 0 not used
1 1 1 not used
DE-EMPHASIS
De-emphasis is a 2-bit value to enable the digital
de-emphasis filter.
Table 10 De-emphasis settings
DE1 DE0
FUNCTION
0 0 no de-emphasis
0 1 de-emphasis, 32 kHz
1 0 de-emphasis, 44.1 kHz
1 1 de-emphasis, 48 kHz
VOLUME CONTROL
The volume control is a 6-bit value to program the volume
attenuation from 0 to −60 dB and −∞ dB in steps of 1 dB.
Table 11 Volume settings
VC5 VC4 VC3 VC2 VC1 VC0 VOLUME (dB)
000000
0
000001
0
000010
000011
−1
−2
::::::
:
110011
110100
−51
110101
110110
−52
110111
111000
−54
111001
111010
−57
111011
111100
111101
−60
111110
111111
−∞
MUTE
Mute is a 1-bit value to enable the digital mute.
Table 12 Mute setting
MT
0 no muting
1 muting
FUNCTION
2000 Apr 18
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet UDA1330ATS.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| UDA1330ATS | Low-cost stereo filter DAC | NXP Semiconductors |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |