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PDF SAF-C161PI Data sheet ( Hoja de datos )
| Número de pieza | SAF-C161PI | |
| Descripción | 16-Bit CMOS Microcontroller | |
| Fabricantes | Infineon Technologies | |
| Logotipo |  |
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Microcontrollers
C166 Family
16-Bit Single-Chip Microcontroller
C161PI
User’s Manual 1999-08
V 1.0
1 page  
C161PI
Table of Contents
Page
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1 The Members of the 16-bit Microcontroller Family . . . . . . . . . . . . . . . . . . 1-2
1.2 Summary of Basic Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.3 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
2
2.1
2.1.1
2.1.2
2.2
2.3
2.4
2.5
Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Basic CPU Concepts and Optimizations . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
High Instruction Bandwidth / Fast Execution . . . . . . . . . . . . . . . . . . . . . 2-3
Programmable Multiple Priority Interrupt System . . . . . . . . . . . . . . . . . 2-7
The On-chip System Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
The On-chip Peripheral Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
Power Management Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
Protected Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
3 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1 Internal ROM Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.2 Internal RAM and SFR Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.3 The On-Chip XRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.4 External Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
3.5 Crossing Memory Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
4 The Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1 Instruction Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.2 Particular Pipeline Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
4.3 Bit-Handling and Bit-Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
4.4 Instruction State Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
4.5 CPU Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
5
5.1
5.1.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
Interrupt and Trap Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Interrupt System Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Interrupt Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
Operation of the PEC Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Prioritization of Interrupt and PEC Service Requests . . . . . . . . . . . . . . . 5-15
Saving the Status during Interrupt Service . . . . . . . . . . . . . . . . . . . . . . . 5-17
Interrupt Response Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18
PEC Response Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21
Interrupt Node Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23
External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24
Trap Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29
6 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.1 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
6.2 Frequency Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6.3 Oscillator Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
User’s Manual
-1
1999-08
5 Page 
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The C164-type devices and some of the C161-type devices are further enhanced by a
flexible power management and form the third generation of the 16-bit controller family.
This power management mechanism provides effective means to control the power that
is consumed in a certain state of the controller and thus allows the minimization of the
overall power consumption with respect to a given application.
A variety of different versions is provided which offer various kinds of on-chip program
memory:
• mask-programmable ROM
• Flash memory
• OTP memory
• ROMless with no non-volatile memory at all.
Also there are devices with specific functional units.
The devices may be offered in different packages, temperature ranges and speed
classes.
More standard and application-specific derivatives are planned and in development.
Note: Not all derivatives will be offered in any temperature range, speed class, package
or program memory variation.
Information about specific versions and derivatives will be made available with the
devices themselves. Contact your Infineon representative for up-to-date material.
Note: As the architecture and the basic features (i.e. CPU core and built in peripherals)
are identical for most of the currently offered versions of the C161PI, the
descriptions within this manual that refer to the “C161PI” also apply to the other
variations, unless otherwise noted.
User’s Manual
1-3
1999-08
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet SAF-C161PI.PDF ] | |
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