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PDF SAF-C161S Data sheet ( Hoja de datos )

Número de pieza SAF-C161S
Descripción 16-Bit CMOS Microcontroller
Fabricantes Infineon Technologies 
Logotipo Infineon Technologies Logotipo



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No Preview Available ! SAF-C161S Hoja de datos, Descripción, Manual

Data Sheet, V1.0, Nov. 2003
C161S
16-Bit Single-Chip Microcontroller
Microcontrollers
Never stop thinking.

1 page




SAF-C161S pdf
16-Bit Single-Chip Microcontroller
C166 Family
C161S
C161S
1 Summary of Features
• High Performance 16-bit CPU with 4-Stage Pipeline
– 80 ns Instruction Cycle Time at 25 MHz CPU Clock
– 400 ns Multiplication (16 × 16 bit), 800 ns Division (32 / 16 bit)
– Enhanced Boolean Bit Manipulation Facilities
– Additional Instructions to Support HLL and Operating Systems
– Register-Based Design with Multiple Variable Register Banks
– Single-Cycle Context Switching Support
– 16 Mbytes Total Linear Address Space for Code and Data
– 1024 Bytes On-Chip Special Function Register Area
• 16-Priority-Level Interrupt System with 30 Sources, Sample-Rate down to 40 ns
• 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via
Peripheral Event Controller (PEC)
• Clock Generation via on-chip PLL (factors 1:1.5/2/2.5/3/4/5),
via prescaler or via direct clock input
• On-Chip Memory Modules: 2 Kbytes On-Chip Internal RAM (IRAM)
• On-Chip Peripheral Modules
– Two Multi-Functional General Purpose Timer Units with 5 Timers
– Two Serial Channels (Sync./Asynchronous and High-Speed-Synchronous)
– On-Chip Real Time Clock
• External Address Space for Code and Data
– Programmable External Bus Characteristics for Different Address Ranges
– Multiplexed or Demultiplexed External Address/Data Buses with 8-bit or 16-bit
Data Bus Width
– Four Programmable Chip-Select Signals
– 4 Mbytes maximum address window size, results in a total external address space
of 16 Mbytes, when all chip-select signal (address windows) are active
• Idle and Power Down Modes with Flexible Power Management
• Programmable Watchdog Timer and Oscillator Watchdog
• Up to 63 General Purpose I/O Lines,
partly with Selectable Input Thresholds and Hysteresis
• Power Supply: the C161S can operate from a 5 V or a 3 V power supply (see Table 1)
• Supported by a Large Range of Development Tools like C-Compilers,
Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers,
Simulators, Logic Analyzer Disassemblers, Programming Boards
• On-Chip Bootstrap Loader
• 80-Pin MQFP Package
Data Sheet
1 V1.0, 2003-11

5 Page





SAF-C161S arduino
C161S
General Device Information
Table 2
Pin Definitions and Functions (cont’d)
Symbol Pin
No.
Input Function
Outp.
PORT1
IO
P1L.0-7 47-54
P1H.0-7 55-62
PORT1 consists of the two 8-bit bidirectional I/O ports P1L
and P1H. It is bit-wise programmable for input or output via
direction bits. For a pin configured as input, the output driver
is put into high-impedance state. PORT1 is used as the
16-bit address bus (A) in demultiplexed bus modes and also
after switching from a demultiplexed bus mode to a
multiplexed bus mode.
RSTIN 65
I/O Reset Input with Schmitt-Trigger characteristics. A low level
at this pin while the oscillator is running resets the C161S. An
internal pull-up resistor permits power-on reset using only a
capacitor connected to VSS.
A spike filter suppresses input pulses < 10 ns. Input pulses
> 100 ns safely pass the filter. The minimum duration for a
safe recognition should be 100 ns + 2 CPU clock cycles.
In bidirectional reset mode (enabled by setting bit BDRSTEN
in register SYSCON) the RSTIN line is internally pulled low
for the duration of the internal reset sequence upon any reset
(HW, SW, WDT). See note below this table.
Note: To let the reset configuration of PORT0 settle and to
let the PLL lock a reset duration of approx. 1 ms is
recommended.
RST 66 O Internal Reset Indication Output. This pin is set to a low level
OUT
when the part is executing either a hardware-, a software- or
a watchdog timer reset. RSTOUT remains low until the EINIT
(end of initialization) instruction is executed.
NMI 67 I
Non-Maskable Interrupt Input. A high to low transition at this
pin causes the CPU to vector to the NMI trap routine. When
the PWRDN (power down) instruction is executed, the NMI
pin must be low in order to force the C161S to go into power
down mode. If NMI is high, when PWRDN is executed, the
part will continue to run in normal mode.
If not used, pin NMI should be pulled high externally.
Data Sheet
7 V1.0, 2003-11

11 Page







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