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PDF ICS8737-11 Data sheet ( Hoja de datos )
| Número de pieza | ICS8737-11 | |
| Descripción | CLOCK GENERATOR | |
| Fabricantes | Integrated Circuit Systems | |
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Integrated
Circuit
Systems, Inc.
ICS8737-11
LOW SKEW ÷1/÷2
DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
GENERAL DESCRIPTION
The ICS8737-11 is a low skew, high performance
,&6 Differential-to-3.3V LVPECL Clock Generator/
HiPerClockS™ Divider and a member of the HiPerClockS™
family of High Performance Clock Solutions from
ICS. The ICS8737-11 has two selectable clock
inputs. The CLK, nCLK pair can accept most standard differ-
ential input levels. The PCLK, nPCLK pair can accept
LVPECL, CML, or SSTL input levels.The clock enable is
internally synchronized to eliminate runt pulses on the
outputs during asynchronous assertion/deassertion of the
clock enable pin.
Guaranteed output and part-to-part skew characteristics
make the ICS8737-11 ideal for clock distribution applications
demanding well defined performance and repeatability.
FEATURES
• 2 divide by 1 differential 3.3V LVPECL outputs;
2 divide by 2 differential 3.3V LVPECL outputs
• Selectable CLK, nCLK or LVPECL clock inputs
• CLK, nCLK pair can accept the following differential input
levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
• PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
• Maximum output frequency up to 650MHz
• Translates any single ended input signal (LVCMOS, LVTTL,
GTL) to LVPECL levels with resistor bias on nCLK input
• Output skew: 60ps (maximum)
• Part-to-part skew: 200ps (maximum)
• Bank skew: Bank A - 20ps (maximum),
Bank B - 35ps (maximum)
• Propagation delay: 1.7ns (maximum)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
BLOCK DIAGRAM
CLK_EN
CLK
nCLK
PCLK
nPCLK
CLK_SEL
MR
D
Q
LE
0
1
÷1
÷2
PIN ASSIGNMENT
QA0
nQA0
QA1
nQA1
QB0
nQB0
QB1
nQB1
VEE 1
20 QA0
CLK_EN 2 19 nQA0
CLK_SEL 3 18 VCC
CLK 4 17 QA1
nCLK 5 16 nQA1
PCLK 6 15 QB0
nPCLK 7 14 nQB0
nc 8
13 VCC
MR 9 12 QB1
VCC 10 11 nQB1
ICS8737-11
20-Lead TSSOP
6.50mm x 4.40mm x 0.92 package body
G Package
Top View
8737AG-11
www.icst.com/products/hiperclocks.html
1
REV. A JULY 13, 2001
1 page  
Integrated
Circuit
Systems, Inc.
ICS8737-11
LOW SKEW ÷1/÷2
DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical
I Input High Current
IH
VIN = VCC = 3.465V
VIN = VCC = 3.465V
IIL Input Low Current
VIN = 0V, VCC = 3.465V
V = 0V, V = 3.465V
IN CC
-5
-150
VPP Peak-to-Peak Input Voltage
0.3
VCMR
Common Mode Input Voltage; NOTE 1, 2
VEE + 1.5
VOH Output High Voltage; NOTE 3
VCC - 1.4
VOL Output Low Voltage; NOTE 3
VCC - 2.0
VSWING Peak-to-Peak Output Voltage Swing
0.65
NOTE 1: Common mode voltage is defined as VIH.
WNOTE 2: For single ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V.
NOTE 3: Outputs terminated with 50 to VCC - 2V.
Maximum
150
5
1
VCC
VCC - 1.0
VCC - 1.7
0.9
Units
µA
µA
µA
µA
V
V
V
V
V
TABLE 5. AC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions Minimum Typical Maximum Units
fMAX Maximum Output Frequency
CLK, nCLK
tPD
Propagation Delay; NOTE 1
PCLK, nPCLK
ģ 650MHz
1.3
1.2
650 MHz
1.7 ns
1.6
tsk(o) Output Skew; NOTE 2, 4
60 ps
tsk(b) Bank Skew; NOTE 4
Bank A
Bank B
20 ps
35
tsk(pp) Part-to-Part Skew; NOTE 3, 4
200 ps
tR Output Rise Time
tF Output Fall Time
odc Output Duty Cycle
20% to 80% @ 50MHz
20% to 80% @ 50MHz
300
300
48
50
All parameters measured at 500MHz unless noted otherwise.
The cycle-to-cycle jitter on the input will equal the jitter on the output. The part does not add jitter.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
700
700
52
ps
ps
%
8737AG-11
www.icst.com/products/hiperclocks.html
5
REV. A JULY 13, 2001
5 Page 
Integrated
Circuit
Systems, Inc.
ICS8737-11
LOW SKEW ÷1/÷2
DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE
θ by Velocity (Linear Feet per Minute)
JA
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
114.5°C/W
73.2°C/W
200
98.0°C/W
66.6°C/W
500
88.0°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8737-11 is: 510
8737AG-11
www.icst.com/products/hiperclocks.html
11
REV. A JULY 13, 2001
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet ICS8737-11.PDF ] | |
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