PDF KM732V789 Data sheet ( Hoja de datos )

Número de pieza	KM732V789
Descripción	128Kx32-Bit Synchronous Pipelined Burst SRAM
Fabricantes	Samsung Semiconductor
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No Preview Available ! KM732V789 128Kx32 Synchronous SRAM Document Title 128Kx32-Bit Synchronous Pipelined Burst SRAM Revision History Rev.No. History 1.0 Initial draft 2.0 change tCYC from 8.5ns to 10.0ns. Modify Rev No. from 0.0 to 1.0. 3.0 Modify DC characteristics( Input Leakage Current test Conditions) form VDD=VSS to VDD to Max. 4.0 Add VDDQ Supply voltage( 2.5V ) 5.0 Remove 119BGA(7x17 Ball Grid Array Package) . Draft Date May . 19. 1998 June . 02. 1998 June. 08. 1998 Dec. 02. 1998 Feb. 10. 1999 Remark Final Final Final Final Final The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques- tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. - 1 - February 1999 Rev 5.0 1 page KM732V789 128Kx32 Synchronous SRAM TRUTH TABLES SYNCHRONOUS TRUTH TABLE CS1 CS2 CS2 ADSP ADSC ADV WRITE CLK ADDRESS ACCESSED HXXXLX X ↑ N/A L LXLXX X ↑ N/A LXHLXX X ↑ N/A L LXXLX X ↑ N/A L XHX LX X ↑ N/A LHL LXX X ↑ External Address LHLHLX L ↑ External Address LHLHLX H ↑ External Address XXXHH L H ↑ Next Address HXXXHL H ↑ Next Address XXXHH L L ↑ Next Address HXXXHL L ↑ Next Address XXXHHH H ↑ Current Address HXXXHH H ↑ Current Address XXXHHH L ↑ Current Address HXXXHH L ↑ Current Address Notes : 1. X means "Don′t Care". 2. The rising edge of clock is symbolized by ↑. 3. WRITE = L means Write operation in WRITE TRUTH TABLE. WRITE = H means Read operation in WRITE TRUTH TABLE. 4. Operation finally depends on status of asynchronous input pins(ZZ and OE). OPERATION Not Selected Not Selected Not Selected Not Selected Not Selected Begin Burst Read Cycle Begin Burst Write Cycle Begin Burst Read Cycle Continue Burst Read Cycle Continue Burst Read Cycle Continue Burst Write Cycle Continue Burst Write Cycle Suspend Burst Read Cycle Suspend Burst Read Cycle Suspend Burst Write Cycle Suspend Burst Write Cycle WRITE TRUTH TABLE GW BW WEa WEb WEc WEd OPERATION HHXXXX READ H L HHHH READ HL LHHH WRITE BYTE a H L H L HH WRITE BYTE b HLHHL L WRITE BYTE c and d HL L L L L WRITE ALL BYTEs LXXXXX WRITE ALL BYTEs Notes : 1. X means "Don′t Care". 2. All inputs in this table must meet setup and hold time around the rising edge of CLK(↑). ASYNCHRONOUS TRUTH TABLE (See Notes 1 and 2): OPERATION ZZ OE I/O STATUS Sleep Mode HX High-Z Read LL LH DQ High-Z Write L X Din, High-Z Deselected LX High-Z Notes 1. X means "Don′t Care". 2. ZZ pin is pulled down internally 3. For write cycles that following read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur. 4. Sleep Mode means power down state of which stand-by current does not depend on cycle time. 5. Deselected means power down state of which stand-by current depends on cycle time. - 5 - February 1999 Rev 5.0 5 Page KM732V789 128Kx32 Synchronous SRAM - 11 - February 1999 Rev 5.0 11 Page

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