|
|
PDF UPD4481162 Data sheet ( Hoja de datos )
| Número de pieza | UPD4481162 | |
| Descripción | (UPD4481162/1182/1322/1362) 8M-BIT ZEROSB SRAM PIPELINED OPERATION | |
| Fabricantes | NEC | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de UPD4481162 (archivo pdf) en la parte inferior de esta página. Total 28 Páginas | ||
|
No Preview Available !
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD4481162, 4481182, 4481322, 4481362
8M-BIT ZEROSBTM SRAM
PIPELINED OPERATION
Description
The µPD4481162 is a 524,288-word by 16-bit, the µPD4481182 is a 524,288-word by 18-bit, the µPD4481322 is a
262,144-word by 32-bit and the µPD4481362 is a 262,144-word by 36-bit ZEROSB static RAM fabricated with
advanced CMOS technology using full CMOS six-transistor memory cell.
The µPD4481162, µPD4481182, µPD4481322 and µPD4481362 are optimized to eliminate dead cycles for read to
write, or write to read transitions. These ZEROSB static RAMs integrate unique synchronous peripheral circuitry, 2-bit
burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the
single clock input (CLK).
The µPD4481162, µPD4481182, µPD4481322 and µPD4481362 are suitable for applications which require
synchronous operation, high speed, low voltage, high density and wide bit configuration, such as buffer memory.
ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State (“Sleep”).
In the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal
operation.
The µPD4481162, µPD4481182, µPD4481322 and µPD4481362 are packaged in 100-pin PLASTIC LQFP with a 1.4
mm package thickness for high density and low capacitive loading.
Features
• Low voltage core supply : VDD = 3.3 ± 0.165 V (-A44, -A50, -A60, -A75, -A44Y, -A50Y, -A60Y, -A75Y)
VDD = 2.5 ± 0.125 V (-C60, -C75, -C60Y, -C75Y)
• Synchronous operation
• Operating temperature : TA = 0 to 70 °C (-A44, -A50, -A60, -A75, -C60, -C75)
TA = −40 to +85 °C (-A44Y, -A50Y, -A60Y, -A75Y, -C60Y, -C75Y)
• 100 percent bus utilization
• Internally self-timed write control
• Burst read / write : Interleaved burst and linear burst sequence
• Fully registered inputs and outputs for pipelined operation
• All registers triggered off positive clock edge
• 3.3V or 2.5V LVTTL Compatible : All inputs and outputs
• Fast clock access time : 2.8 ns (225 MHz), 3.2 ns (200 MHz), 3.5 ns (167 MHz) , 4.2 ns (133 MHz)
• Asynchronous output enable : /G
• Burst sequence selectable : MODE
• Sleep mode : ZZ (ZZ = Open or Low : Normal operation)
• Separate byte write enable : /BW1 to /BW4 (µPD4481322 and µPD4481362)
/BW1 and /BW2 (µPD4481162 and µPD4481182)
• Three chip enables for easy depth expansion
• Common I/O using three state outputs
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. M15562EJ3V0DS00 (3rd edition)
Date Published December 2002 NS CP(K)
Printed in Japan
The mark shows major revised points.
2001
1 page  
µPD4481162, 4481182, 4481322, 4481362
Pin Identifications
[µPD4481162GF, µPD4481182GF]
Symbol
Pin No.
Description
A0 to A18
37, 36, 35, 34, 33, 32, 100, 99, 82, 81,
44, 45, 46, 47, 48, 49, 50, 83, 80
Synchronous Address Input
I/O1 to I/O16
I/OP1, NC Note
I/OP2, NC Note
58, 59, 62, 63, 68, 69, 72, 73, 8, 9, 12, 13, Synchronous Data In,
18, 19, 22, 23
Synchronous / Asynchronous Data Out
74 Synchronous Data In (Parity),
24 Synchronous / Asynchronous Data Out (Parity)
ADV
85
Synchronous Address Load / Advance Input
/CE, CE2, /CE2
98, 97, 92
Synchronous Chip Enable Input
/WE 88
Synchronous Write Enable Input
/BW1, /BW2
93, 94
Synchronous Byte Write Enable Input
/G 86
Asynchronous Output Enable Input
CLK 89
Clock Input
/CKE
87
Synchronous Clock Enable Input
MODE
ZZ
31
64
Asynchronous Burst Sequence Select Input
Have to tied to VDD or VSS during normal operation
Asynchronous Power Down State Input
VDD
14, 15, 16, 41, 65, 66, 91
Power Supply
VSS 17, 40, 67, 90
Ground
VDDQ
VSSQ
4, 11, 20, 27, 54, 61, 70, 77
5, 10, 21, 26, 55, 60, 71, 76
Output Buffer Power Supply
Output Buffer Ground
NC 1, 2, 3, 6, 7, 25, 28, 29, 30, 38, 39, 42, 43, No Connection
51, 52, 53, 56, 57, 75, 78, 79, 84, 95, 96
Note NC (No Connection) is used in the µPD4481162GF.
I/OP1 and I/OP2 are used in the µPD4481182GF.
Data Sheet M15562EJ3V0DS
5
5 Page 
µPD4481162, 4481182, 4481322, 4481362
Asynchronous Truth Table
Operation
Read Cycle
Read Cycle
Write Cycle
Deselected
Remark × : don’t care
/G
L
H
×
×
I/O
Dout
High-Z
High-Z, Din
High-Z
Synchronous Truth Table
Operation
/CE CE2 /CE2 ADV /WE /BWs /CKE CLK
I/O Address Note
Deselected
Deselected
H × × L × × L L → H High-Z None
× L × L × × L L → H High-Z None
1
1
Deselected
× × H L × × L L → H High-Z None
1
Continue Deselected
× × × H × × L L → H High-Z None
1
Read Cycle / Begin Burst
L H L L H × L L → H Dout External
Read Cycle / Continue Burst
× × × H × × L L → H Dout
Next
Write Cycle / Begin Burst
L H L L L L L L → H Din External
Write Cycle / Continue Burst
××
×H×
L L L→H
Din
Next
Write Cycle / Write Abort
L H L L L H L L → H High-Z External
Write Cycle / Write Abort
× × × H × H L L → H High-Z
Next
Stall / Ignore Clock Edge
× × × × × × H L→H
−
Current
2
Notes
1. Deselect status is held until new “Begin Burst” entry.
2. If an Ignore Clock Edge command occurs during a read operation, the I/O bus will remain active (low
impedance). If it occurs during a write cycle, the bus will remain high impedance. No write operation will
be performed during the Ignore Clock Edge cycle.
Remarks 1. × : don’t care
2. /BWs = L means any one or more byte write enables (/BW1, /BW2, /BW3 or /BW4) are LOW.
/BWs = H means all byte write enables (/BW1, /BW2, /BW3 or /BW4) are HIGH.
Data Sheet M15562EJ3V0DS
11
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet UPD4481162.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| UPD4481161 | (UPD4481161/1181/1321/1361) 8M-BIT ZEROSB SRAM FLOW THROUGH OPERATION | NEC |
| UPD4481162 | (UPD4481162/1182/1322/1362) 8M-BIT ZEROSB SRAM PIPELINED OPERATION | NEC |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |