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PDF UPD4482321 Data sheet ( Hoja de datos )

Número de pieza UPD4482321
Descripción (UPD4482161/2181/2321/2361) 8M-BIT CMOS SYNCHRONOUS FAST SRAM FLOW THROUGH OPERATION
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD4482161, 4482181, 4482321, 4482361
8M-BIT CMOS SYNCHRONOUS FAST SRAM
FLOW THROUGH OPERATION
Description
The µPD4482161 is a 524,288-word by 16-bit, the µPD4482181 is a 524,288-word by 18-bit, the µPD4482321 is a
262,144-word by 32-bit and the µPD4482361 is a 262,144-word by 36-bit synchronous static RAM fabricated with
advanced CMOS technology using Full-CMOS six-transistor memory cell.
The µPD4482161, µPD4482181, µPD4482321 and µPD4482361 integrate unique synchronous peripheral circuitry, 2-bit
burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the single
clock input (CLK).
The µPD4482161, µPD4482181, µPD4482321 and µPD4482361 are suitable for applications which require synchronous
operation, high speed, low voltage, high density and wide bit configuration, such as cache and buffer memory.
ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State (“Sleep”). In
the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal operation.
The µPD4482161, µPD4482181, µPD4482321 and µPD4482361 are packaged in 100-pin PLASTIC LQFP with a 1.4
mm package thickness for high density and low capacitive loading.
Features
3.3 V or 2.5 V core supply
Synchronous operation
Operating temperature : TA = 0 to 70 °C (-A65, -A75, -A85, -C75, -C85)
TA = 40 to +85 °C (-A65Y, -A75Y, -A85Y, -C75Y, -C85Y)
Internally self-timed write control
Burst read / write : Interleaved burst and linear burst sequence
Fully registered inputs for flow through operation
All registers triggered off positive clock edge
3.3 V or 2.5 V LVTTL Compatible : All inputs and outputs
Fast clock access time : 6.5 ns (133 MHz), 7.5 ns (117 MHz), 8.5 ns (100 MHz)
Asynchronous output enable : /G
Burst sequence selectable : MODE
Sleep mode : ZZ (ZZ = Open or Low : Normal operation)
Separate byte write enable : /BW1 to /BW4, /BWE (µPD4482321, µPD4482361)
/BW1, /BW2, /BWE (µPD4482161, µPD4482181)
Global write enable : /GW
Three chip enables for easy depth expansion
Common I/O using three state outputs
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. M14521EJ3V0DS00 (3rd edition)
Date Published December 2002 NS CP(K)
Printed in Japan
The mark  shows major revised points.
2000

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UPD4482321 pdf
µPD4482161, 4482181, 4482321, 4482361
Pin Identification (µPD4482161GF, µPD4482181GF)
Symbol
Pin No.
Description
A0 to A18
37, 36, 35, 34, 33, 32, 100, 99, 82, Synchronous Address Input
81, 44, 45, 46, 47, 48, 49, 50, 43, 80
I/O1 to I/O16
58, 59, 62, 63, 68, 69, 72, 73, 8, 9, Synchronous Data In,
I/OP1, NC Note
I/OP2, NC Note
12, 13, 18, 19, 22, 23
74
24
Synchronous / Asynchronous Data Out
Synchronous Data In (Parity),
Synchronous / Asynchronous Data Out (Parity)
/ADV
83
Synchronous Burst Address Advance Input
/AP 84
Synchronous Address Status Processor Input
/AC 85
Synchronous Address Status Controller Input
/CE, CE2, /CE2
98, 97, 92
Synchronous Chip Enable Input
/BW1, /BW2, /BWE
93, 94, 87
Synchronous Byte Write Enable Input
/GW 88
Synchronous Global Write Input
/G 86
Asynchronous Output Enable Input
CLK 89
Clock Input
MODE
31
Asynchronous Burst Sequence Select Input
Do not change state during normal operation
ZZ 64
Asynchronous Power Down State Input
VDD 15, 41, 65, 91
Power Supply
VSS 17, 40, 67, 90
Ground
VDDQ
4, 11, 20, 27, 54, 61, 70, 77
Output Buffer Power Supply
VSSQ
5, 10, 21, 26, 55, 60, 71, 76
Output Buffer Ground
NC 1, 2, 3, 6, 7, 14, 16, 25, 28, 29, 30, No Connection
38, 39, 42, 51, 52, 53, 56, 57, 66, 75,
78, 79, 95, 96
Note NC (No Connection) is used in the µPD4482161GF.
I/OP1 and I/OP2 are used in the µPD4482181GF.
Data Sheet M14521EJ3V0DS
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UPD4482321 arduino
µPD4482161, 4482181, 4482321, 4482361
Partial Truth Table for Write Enables
[µPD4482161, µPD4482181]
Operation
Read Cycle
Read Cycle
Write Cycle / Byte 1 (I/O [1:8], I/OP1)
Write Cycle / Byte 2 (I/O [9:16], I/OP2)
Write Cycle / All Bytes
Write Cycle / All Bytes
Remark × : don’t care
[µPD4482321, µPD4482361]
Operation
Read Cycle
Read Cycle
Write Cycle / Byte 1 (I/O [1:8], I/OP1)
Write Cycle / Byte 2 (I/O [9:16], I/OP2)
Write Cycle / Byte 3 (I/O [17:24], I/OP3)
Write Cycle / Byte 4 (I/O [25:32], I/OP4)
Write Cycle / All Bytes
Write Cycle / All Bytes
Remark × : don’t care
/GW
/BWE
/BW1
/BW2
HH× ×
H L HH
HL LH
HLHL
HL LL
L×××
/GW
/BWE
/BW1
/BW2
/BW3
/BW4
HH× × × ×
H L HHHH
H L L HHH
H L H L HH
HL HHLH
HL HHHL
HL LL LL
L×××××
ZZ (Sleep) Truth Table
ZZ
0.2 V
Open
VDD 0.2 V
Chip Status
Active
Active
Sleep
Data Sheet M14521EJ3V0DS
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