PDF UPD4481181 Data sheet ( Hoja de datos )

Número de pieza	UPD4481181
Descripción	(UPD4481161/1181/1321/1361) 8M-BIT ZEROSB SRAM FLOW THROUGH OPERATION
Fabricantes	NEC
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No Preview Available ! DATA SHEET MOS INTEGRATED CIRCUIT µPD4481161, 4481181, 4481321, 4481361 8M-BIT ZEROSBTM SRAM FLOW THROUGH OPERATION Description The µPD4481161 is a 524,288-word by 16-bit, the µPD4481181 is a 524,288-word by 18-bit, the µPD4481321 is a 262,144-word by 32-bit and the µPD4481361 is a 262,144-word by 36-bit ZEROSB static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. The µPD4481161, µPD4481181, µPD4481321 and µPD4481361 are optimized to eliminate dead cycles for read to write, or write to read transitions. These ZEROSB static RAMs integrate unique synchronous peripheral circuitry, 2-bit burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the single clock input (CLK). The µPD4481161, µPD4481181, µPD4481321 and µPD4481361 are suitable for applications which require synchronous operation, high speed, low voltage, high density and wide bit configuration, such as buffer memory. ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State (“Sleep”). In the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal operation. The µPD4481161, µPD4481181, µPD4481321 and µPD4481361 are packaged in 100-pin PLASTIC LQFP with a 1.4 mm package thickness for high density and low capacitive loading. Features • Low voltage core supply : VDD = 3.3 ± 0.165 V (-A65, -A75, -A85, -A65Y, -A75Y, -A85Y) VDD = 2.5 ± 0.125 V (-C75, -C85, -C75Y, -C85Y) • Synchronous operation • Operating temperature : TA = 0 to 70 °C (-A65, -A75, -A85, -C75, -C85) TA = −40 to +85 °C (-A65Y, -A75Y, -A85Y, -C75Y, -C85Y) • 100 percent bus utilization • Internally self-timed write control • Burst read / write : Interleaved burst and linear burst sequence • Fully registered inputs and outputs for flow through operation • All registers triggered off positive clock edge • 3.3V or 2.5V LVTTL Compatible : All inputs and outputs • Fast clock access time : 6.5 ns (133 MHz), 7.5 ns (117 MHz), 8.5 ns (100 MHz) • Asynchronous output enable : /G • Burst sequence selectable : MODE • Sleep mode : ZZ (ZZ = Open or Low : Normal operation) • Separate byte write enable : /BW1 to /BW4 (µPD4481321 and µPD4481361) /BW1 and /BW2 (µPD4481161 and µPD4481181) • Three chip enables for easy depth expansion • Common I/O using three state outputs The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. M15561EJ3V0DS00 (3rd edition) Date Published December 2002 NS CP(K) Printed in Japan The mark shows major revised points. 2001 1 page µPD4481161, 4481181, 4481321, 4481361 Pin Identifications [µPD4481161GF, µPD4481181GF] Symbol Pin No. A0 to A18 37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48, 49, 50, 83, 80 I/O1 to I/O16 58, 59, 62, 63, 68, 69, 72, 73, 8, 9, 12, 13, I/OP1, NC Note I/OP2, NC Note 18, 19, 22, 23 74 24 ADV 85 /CE, CE2, /CE2 98, 97, 92 /WE 88 /BW1, /BW2 93, 94 /G 86 CLK 89 /CKE 87 MODE 31 ZZ VDD VSS VDDQ VSSQ NC 64 15, 16, 41, 65, 91 14, 17, 40, 66, 67, 90 4, 11, 20, 27, 54, 61, 70, 77 5, 10, 21, 26, 55, 60, 71, 76 1, 2, 3, 6, 7, 25, 28, 29, 30, 38, 39, 42, 43, 51, 52, 53, 56, 57, 75, 78, 79, 84, 95, 96 Description Synchronous Address Input Synchronous Data In, Synchronous / Asynchronous Data Out Synchronous Data In (Parity), Synchronous / Asynchronous Data Out (Parity) Synchronous Address Load / Advance Input Synchronous Chip Enable Input Synchronous Write Enable Input Synchronous Byte Write Enable Input Asynchronous Output Enable Input Clock Input Synchronous Clock Enable Input Asynchronous Burst Sequence Select Input Have to tied to VDD or VSS during normal operation Asynchronous Power Down State Input Power Supply Ground Output Buffer Power Supply Output Buffer Ground No Connection Note NC (No Connection) is used in the µPD4481161GF. I/OP1 and I/OP2 are used in the µPD4481181GF. Data Sheet M15561EJ3V0DS 5 5 Page µPD4481161, 4481181, 4481321, 4481361 Asynchronous Truth Table Operation /G Read Cycle L Read Cycle H Write Cycle Deselected × × Remark × : don’t care I/O Dout High-Z High-Z, Din High-Z Synchronous Truth Table Operation /CE CE2 /CE2 ADV /WE /BWs /CKE CLK I/O Address Note Deselected Deselected Deselected Continue Deselected H × × L × × L L → H High-Z None 1 × L × L × × L L → H High-Z None 1 × × H L × × L L → H High-Z None 1 × × × H × × L L → H High-Z None 1 Read Cycle / Begin Burst L H L L H × L L → H Dout External Read Cycle / Continue Burst × × × H × × L L → H Dout Next Write Cycle / Begin Burst L H L L L L L L → H Din External Write Cycle / Continue Burst × × ×H× L L L→H Din Next Write Cycle / Write Abort L H L L L H L L → H High-Z External Write Cycle / Write Abort × × × H × H L L → H High-Z Next Stall / Ignore Clock Edge × × × × × × H L→H − Current 2 Notes 1. Deselect status is held until new “Begin Burst” entry. 2. If an Ignore Clock Edge command occurs during a read operation, the I/O bus will remain active (low impedance). If it occurs during a write cycle, the bus will remain high impedance. No write operation will be performed during the Ignore Clock Edge cycle. Remarks 1. × : don’t care 2. /BWs = L means any one or more byte write enables (/BW1, /BW2, /BW3 or /BW4) are LOW. /BWs = H means all byte write enables (/BW1, /BW2, /BW3 or /BW4) are HIGH. Data Sheet M15561EJ3V0DS 11 11 Page

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