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PDF KMM5324100CK Data sheet ( Hoja de datos )
| Número de pieza | KMM5324100CK | |
| Descripción | (KMM5324100CK / KMM5324000CK) 4MBx32 DRAM Simm Using 4MBx4 | |
| Fabricantes | Samsung Semiconductor | |
| Logotipo |  |
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DRAM MODULE
KMM5324000CK/CKG
KMM5324100CK/CKG
KMM5324000CK/CKG & KMM5324100CK/CKG with Fast Page Mode
4M x 32 DRAM SIMM using 4Mx4, 4K/2K Refresh, 5V
GENERAL DESCRIPTION
The Samsung KMM53240(1)00CK is a 4Mx32bits Dynamic
RAM high density memory module. The Samsung
KMM53240(1)00CK consists of eight CMOS 4Mx4bits DRAMs
in 24-pin SOJ package mounted on a 72-pin glass-epoxy sub-
strate. A 0.1 or 0.22uF decoupling capacitor is mounted on the
printed circuit board for each DRAM. The KMM53240(1)00CK
is a Single In-line Memory Module with edge connections and
is intended for mounting into 72 pin edge connector sockets.
PERFORMANCE RANGE
Speed
tRAC
tCAC
tRC
-5
50ns
13ns
90ns
-6
60ns
15ns
130ns
FEATURES
• Part Identification
- KMM5324000CK(4096 cycles/64ms Ref, SOJ, Solder)
- KMM5324000CKG(4096 cycles/64ms Ref, SOJ, Gold)
- KMM5324100CK(2048 cycles/32ms Ref, SOJ, Solder)
- KMM5324100CKG(2048 cycles/32ms Ref, SOJ, Gold)
• Fast Page Mode Operation
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• TTL compatible inputs and outputs
• Single +5V±10% power supply
• JEDEC standard PDPin & pinout
• PCB : Height(1000mil), single sided component
PIN CONFIGURATIONS
Pin Symbol Pin Symbol
1 VSS 37 NC
2
DQ0
38
NC
3
DQ16
39
VSS
4
DQ1
40 CAS0
5 DQ17 41 CAS2
6
DQ2
42 CAS3
7 DQ18 43 CAS1
8
DQ3
44 RAS0
9
DQ19
45 Res(RAS1)
10 Vcc 46 NC
11 NC 47
W
12 A0 48 NC
13 A1 49 DQ8
14 A2 50 DQ24
15 A3 51 DQ9
16 A4 52 DQ25
17 A5 53 DQ10
18 A6 54 DQ26
19 A10 55 DQ11
20 DQ4 56 DQ27
21 DQ20 57 DQ12
22 DQ5 58 DQ28
23 DQ21 59
VCC
24 DQ6 60 DQ29
25 DQ22 61 DQ13
26 DQ7 62 DQ30
27 DQ23 63 DQ14
28 A7 64 DQ31
29 A11 65 DQ15
30 Vcc 66 NC
31 A8 67 PD1
32 A9 68 PD2
33 Res(RAS1) 69
PD3
34 RAS0 70
PD4
35 NC 71 NC
36 NC 72 Vss
PIN NAMES
Pin Name
A0 - A11
A0 - A10
DQ0 - DQ31
W
RAS0
CAS0 - CAS3
PD1 -PD4
Vcc
Vss
NC
Function
Address Inputs(4K Ref)
Address Inputs(2K Ref)
Data In/Out
Read/Write Enable
Row Address Strobe
Column Address Strobe
Presence Detect
Power(+5V)
Ground
No Connection
PRESENCE DETECT PINS (Optional)
Pin
50NS
60NS
PD1 Vss Vss
PD2 NC
NC
PD3 Vss
NC
PD4 Vss
NC
* Pin connection changing available
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
* NOTE : A11 is used for only KMM5324000CK/CKG (4K ref.)
1 page  
DRAM MODULE
KMM5324000CK/CKG
KMM5324100CK/CKG
AC CHARACTERISTICS (0°C≤TA≤70°C, VCC=5.0V±10%. See notes 1,2.)
Test condition : Vih/Vil=2.4/0.8V, Voh/Vol=2.4/0.4V, Output loading CL=100pF
Parameter
Access time from CAS precharge
Fast page mode cycle time
CAS precharge time(Fast page cycle)
RAS pulse width(Fast page cycle)
W to RAS precharge time(C-B-R refresh)
W to RAS hold time(C-B-R refresh)
CAS precharge(C-B-R counter test)
Symbol
tCPA
tPC
tCP
tRASP
tWRP
tWRH
tCPT
-5
Min Max
30
35
10
50 200K
10
10
20
Min
40
10
60
10
10
20
-6
Max
35
200K
Unit Note
ns 3
ns
ns
ns
ns
ns
ns
NOTES
1. An initial pause of 200us is required after power-up followed
by any 8 RAS-only or CAS-before-RAS refresh cycles before
proper device operation is achieved.
2. VIH(min) and VIL(max) are reference levels for measuring
timing of input signals. Transition times are measured
between VIH(min) and VIL(max) and are assumed to be 5ns
for all inputs.
3. Measured with a load equivalent to 2 TTL loads and 100pF.
7. tWCS is non-restrictive operating parameter. It is included in
the data sheet as electrical characteristics only. If
tWCS≥tWCS(min), the cycle is an early write cycle and the data
out pin will remain high impedance for the duration of the
cycle.
8. Either tRCH or tRRH must be satisfied for a read cycle.
9. These parameter are referenced to the CAS leading edge in
early write cycles.
4. Operation within the tRCD(max) limit insures that tRAC(max)
can be met. tRCD(max) is specified as a reference point only.
If tRCD is greater than the specified tRCD(max) limit, then
access time is controlled exclusively by tCAC.
10. Operation within the tRAD(max) limit insures that tRAC(max)
can be met. tRAD(max) is specified as reference point only. If
tRAD is greater than the specified tRAD(max) limit, then
access time is controlled by tAA.
5. Assumes that tRCD≥tRCD(max).
6. This parameter defines the time at which the output achieves
the open circuit condition and is not referenced to VOH or
VOL.
5 Page 
DRAM MODULE
HIDDEN REFRESH CYCLE ( READ )
KMM5324000CK/CKG
KMM5324100CK/CKG
VIH -
RAS
VIL -
VIH -
CAS
VIL -
VIH -
A
VIL -
VIH -
W
VIL -
VOH -
DQ
VOL -
tRC
tRAS
tRC
tRP tRAS
tRP
tCRP
tRCD
tRSH
tASR
tRAD
tRAH
tASC
ROW
ADDRESS
tCAH
COLUMN
ADDRESS
tRCS
tRRH
tCHR
tWRH
tWRP
OPEN
tRAC
tAA
tCAC
tCLZ
tOFF
DATA-OUT
Don′t care
Undefined
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet KMM5324100CK.PDF ] | |
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