PDF KMM5322104CKU Data sheet ( Hoja de datos )

Número de pieza	KMM5322104CKU
Descripción	2MB X 32 DRAM Simm Using 2MB X 8
Fabricantes	Samsung Semiconductor
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No Preview Available ! DRAM MODULE KMM5322104CKU/CKUG KMM5322104CKU/CKUG Fast Page Mode with Extended Data Out 2M x 32 DRAM SIMM using 2Mx8 , 2K Refresh, 5V GENERAL DESCRIPTION The Samsung KMM5322104CKU is a 2Mx32bits Dynamic RAM high density memory module. The Samsung KMM5322104CKU consists of four CMOS 2Mx8bits DRAMs in 28-pin SOJ package mounted on a 72-pin glass-epoxy sub- strate. A 0.1 or 0.22uF decoupling capacitor is mounted on the printed circuit board for each DRAM. The KMM5322104CKU is a Single In-line Memory Module with edge connections and is intended for mounting into 72 pin edge connector sockets. PERFORMANCE RANGE Speed tRAC tCAC tRC tHPC -5 50ns 13ns 90ns 25ns -6 60ns 15ns 110ns 30ns FEATURES • Part Identification - KMM5322104CKU(2048 cycles/32ms Ref, SOJ, Solder) - KMM5322104CKUG(2048 cycles/32ms Ref, SOJ, Gold) • Fast Page Mode with Extended Data Out • CAS-before-RAS refresh capability • RAS-only and Hidden refresh capability • TTL compatible inputs and outputs • Single +5V±10% power supply • JEDEC standard PDPin & pinout • PCB : Height(1000mil), single sided component PIN CONFIGURATIONS Pin Symbol Pin Symbol 1 VSS 37 NC 2 DQ0 38 NC 3 DQ18 39 Vss 4 DQ1 40 CAS0 5 DQ19 41 CAS2 6 DQ2 42 CAS3 7 DQ20 43 CAS1 8 DQ3 44 RAS0 9 DQ21 45 Res(RAS1) 10 Vcc 46 NC 11 NC 47 W 12 A0 48 NC 13 A1 49 DQ9 14 A2 50 DQ27 15 A3 51 DQ10 16 A4 52 DQ28 17 A5 53 DQ11 18 A6 54 DQ29 19 A10 55 DQ12 20 DQ4 56 DQ30 21 DQ22 57 DQ13 22 DQ5 58 DQ31 23 DQ23 59 Vcc 24 DQ6 60 DQ32 25 DQ24 61 DQ14 26 DQ7 62 DQ33 27 DQ25 63 DQ15 28 A7 64 DQ34 29 Res(A11) 65 DQ16 30 Vcc 66 NC 31 A8 67 PD1 32 A9 68 PD2 33 Res(RAS1) 69 PD3 34 RAS0 70 PD4 35 NC 71 NC 36 NC 72 Vss PIN NAMES Pin Name A0 - A10 DQ0 - DQ31 W RAS0 CAS0 - CAS3 PD1 -PD4 Vcc Vss NC Res Function Address Inputs Data In/Out Read/Write Enable Row Address Strobe Column Address Strobe Presence Detect Power(+5V) Ground No Connection Reserved Pin PRESENCE DETECT PINS (Optional) Pin 50NS 60NS PD1 NC PD2 NC PD3 Vss PD4 Vss NC NC NC NC * Pin connection changing available SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. 1 page DRAM MODULE KMM5322104CKU/CKUG AC CHARACTERISTICS (0°C≤TA≤70°C, VCC=5.0V±10%. See notes 1,2.) Test condition : Vih/Vil=2.4/0.8V, Voh/Vol=2.0/0.8V, output loading CL=100pF Parameter Symbol Access time from CAS precharge Hyper page mode cycle time CAS precharge time from (Hyper Page Cycle) RAS pulse width (Hyper Page Cycle) RAS hold time from CAS precharge W to RAS precharge time (C-B-R refresh) W to RAS hold time (C-B-R refresh) Output data hold time Output buffer turn off delay from RAS Output buffer turn off delay from W W to data delay W pulse width (Hyper Page Cycle) tCPA tHPC tCP tRASP tRHCP tWRP tWRH tDOH tREZ tWEZ tWED tWPE -5 Min Max 30 25 8 50 200K 30 10 10 5 3 13 3 13 15 5 -6 Min Max 35 30 10 60 200K 35 10 10 5 3 15 3 15 15 5 Unit ns ns ns ns ns ns ns ns ns ns ns ns Note 3 13 6,11,12 6,11 NOTES 1. An initial pause of 200us is required after power-up followed by any 8 RAS-only or CAS-before-RAS refresh cycles before proper device operation is achieved. 2. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs. 3. Measured with a load equivalent to 2 TTL loads and 100pF. 8. Either tRCH or tRRH must be satisfied for a read cycle. 9. These parameters are referenced to the CAS leading edge in early write cycles and to the W leading edge in read-write cycles. 10. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as reference point only. If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA. 4. Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. 5. Assumes that tRCD≥tRCD(max). 6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to VOH or VOL. 11. tCEZ(max), tREZ(max), tWEZ(max) and tOEZ(max) define the time at which the output achieves the open circuit condition and are not referenced to output voltage level. 12. If RAS goes to high before CAS high going, the open circuit condtion of the output is achieved by CAS high going. If CAS goes to high before RAS high going, the open circuit condtion of the output is achieved by RAS high going. 13. tASC≥tCP min 7. tWCS is non-restrictive operating parameter. It is included in the data sheet as electrical characteristics only. If tWCS≥tWCS(min), the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle. 5 Page DRAM MODULE HIDDEN REFRESH CYCLE ( READ ) KMM5322104CKU/CKUG VIH - RAS VIL - VIH - CAS VIL - VIH - A VIL - VIH - W VIL - VOH - DQ VOL - tRC tRAS tRP tRC tRAS tCRP tRCD tRSH tASR tRAD tRAH tASC ROW ADDRESS tCAH COLUMN ADDRESS tRCS tRRH tCHR tWRH tWRP tRP OPEN tAA tCLZ tRAC tCAC tREZ tWEZ DATA-OUT tCEZ Don′t care Undefined 11 Page

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