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PDF DS1963S Data sheet ( Hoja de datos )
| Número de pieza | DS1963S | |
| Descripción | SHA iButton | |
| Fabricantes | Dallas Semiconducotr | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de DS1963S (archivo pdf) en la parte inferior de esta página. Total 37 Páginas | ||
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www.iButton.com
DS1963S
SHA iButton
SPECIAL FEATURES
§ 4096 bits of read/write nonvolatile (NV)
memory organized as 16 pages of 256 bits
each
§ Eight memory pages with individual 64-bit
secrets and 32-bit read-only non rolling-over
page write cycle counters
§ Secrets are write-only and have their own
individual write cycle counters
§ On-chip 512-bit SHA-1 (FIPS 180-1,
ISO/IEC 10118-3) engine to compute a 160-
bit Message Authentication Codes (MAC)
and generate page secrets
§ Device can operate as roaming iButton® or
as coprocessor for a host computer
§ 256–bit scratchpad ensures integrity of data
transfer
§ On-chip 16-bit CRC generator for
safeguarding data transfers
§ Overdrive mode boosts communication
speed to 125 kbits per second
§ Operating temperature range from -20°C to
+85°C
§ Over 10 years of data retention
§ Button shape is self-aligning with cup-
shaped probes
§ Durable stainless steel case engraved with
registration number withstands harsh
environments
§ Easily affixed with self-stick adhesive
backing, latched by its flange, or locked with
a ring pressed onto its rim
§ Presence detector acknowledges when reader
first applies voltage
§ Meets UL#913 (4th Edit.); Intrinsically Safe
Apparatus, Approved under Entity Concept
for use in Class I, Division 1, Group A, B, C
and D Locations (application pending)
F5 MicroCan
5.89
0.51
â
16.25
05100000FBCâ521B8
1-Wireâ
17.35
COMMON iButton FEATURES
§ Unique, factory–lasered and tested 64-bit
registration number (8-bit family code
+ 48-bit serial number + 8-bit CRC tester)
assures absolute traceability because no two
parts are alike
§ Multidrop controller for MicroLAN
§ Digital identification and information by
momentary contact
§ Chip-based data carrier compactly stores
information
§ Data can be accessed while affixed to object
§ Economically communicates to host with a
single digital signal at 15.4 kbits per second
§ Standard 16 mm diameter and 1-Wire®
protocol ensure compatibility with iButton
Device family
IO GND
All dimensions are shown in millimeters
ORDERING INFORMATION
DS1963S F5 MicroCan
EXAMPLES OF ACCESSORIES
DS9096P Self-Stick Adhesive Pad
DS9101
Multipurpose Clip
DS9093RA Mounting Lock Ring
DS9093A Snap-In Fob
DS9092
iButton Probe
iButton and 1-Wire are registered trademarks of Dallas Semiconductor.
1 of 37
021704
1 page  
HIERARCHCAL STRUCTURE FOR 1-WIRE PROTOCOL Figure 2
Bus
Master
1-Wire Bus
Other
Devices
DS1963S
Command
Level
1-Wire ROM Function
Commands (see Figure 10)
DS1963S specific
Memory Function
Commands (see Figure 7)
DS1963S
Available
Commands
Read ROM
Match ROM
Search ROM
Skip ROM
Resume
Overdrive Skip
Overdrive Match
Write Scratchpad
Read Scratchpad
Copy Scratchpad
Match Scratchpad
Erase Scratchpad
Read Memory
Read Authenti-
cated Page
Compute SHA
Data Fields
Affected
64-bit ROM, RC-Flag
64-bit ROM, RC-Flag
64-bit ROM, RC-Flag
RC-Flag
RC-Flag
64-bit ROM, RC-Flag, OD-Flag
64-bit ROM, RC-Flag, OD-Flag
256-bit Scratchpad, Flags
256-bit Scratchpad, HIDE Flag
Data Memory, Secrets Memory,
W/C Counter, Flags
160 bits of Scratchpad, Flags
256-bit Scratchpad, Flags
Data Memory, Flags
Data Memory, W/C Counters of
Memory Page and Secret, Secret, 64-
bit ROM Registration Number, 160 bits
of Scratchpad, Flags, PRNG Counter
Several of the following Items,
depending on selected Sub-Function:
Data Memory, W/C Counter of
Memory Page, Secret, 64-bit ROM
Registration Number, Scratchpad,
Flags, PRNG Counter
64-BIT LASERED ROM Figure 3
MSB
8-Bit CRC Code
MSB
LSB MSB
48-Bit Serial Number
LSB
8-Bit Family Code (18h)
LSB MSB
LSB
5 of 37
5 Page 
DS1963S
command, the master must provide the 2-byte target address. After these 2 bytes, the master reads data
beginning from the target address and may continue until the end of the PRNG counter and beyond. The
12 bytes following the PRNG counter are undefined. If the master continues reading the result will be
logic 1’s. It is important to realize that the target address registers will point to the last byte read. The
ending offset/data status byte is unaffected.
The hardware of the DS1963S provides a means to accomplish error-free writing to the memory section.
To safeguard reading data in the 1-Wire environment and to simultaneously speed up data transfers, it is
recommended to packetize data into data packets of the size of one memory page each. Such a packet
would typically store a master-calculated 16-bit CRC with each page of data to insure rapid, error-free
data transfers that eliminate having to read a page multiple times to determine if the received data is
correct or not. (See Application Note 114 for the recommended file structure, which is also referred to as
TMEX Format.)
Erase Scratchpad [C3h]
The purpose of this command is to clear the HIDE flag and to wipe out data that might have been left in
the scratchpad from a previous operation. After having issued the command code the bus master transmits
a target address, as with the write scratchpad command, but no data. Next the whole scratchpad will be
automatically filled with FFh bytes, regardless of the target address. This process takes approximately 32
µs during which the master reads 1’s. After this the master reads a pattern of alternating 0’s and 1’s
indicating that the command has completed. The master must read at least 8 bits of this alternating
pattern. Otherwise the device might not properly respond to a subsequent Reset Pulse.
Match Scratchpad [3Ch]
SHA-1 MACs calculated by the DS1963S are written into the scratchpad. Some calculations such as
those done by the Authenticate Host or Validate Data Page function cause the HIDE flag to be set as well.
The Match Scratchpad command allows this data to be checked without making it publicly readable. The
command compares the 160-bit Message Authentication Code which is found in scratchpad locations
8 through 27 after a SHA computation, as described in the sections “SHA-1 Computation Algorithm” and
“SHA-1 Output Message Formats”, to the result that the master has computed by its own means. After the
master has issued the Match Scratchpad command code it transmits 1 byte after another starting with byte
8 and ending with byte 27. If all bytes match, the master will read a pattern of alternating 0’s and 1’s. If in
addition the AUTH-flag was set, the MATCH-flag will be set. If the comparison was not successful the
master will read all 1’s. The master must read at least 8 bits after having received the inverted CRC16.
Otherwise the device might not properly respond to a subsequent Reset Pulse.
11 of 37
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| PDF Descargar | [ Datasheet DS1963S.PDF ] | |
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