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Número de pieza M44C090-H
Descripción (M44C890-H / M44C090-H) Low Current Microcontroller for Wireless Communication
Fabricantes ATMEL Corporation 
Logotipo ATMEL Corporation Logotipo



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M44C090-H
M44C890-H
Low-Current Microcontroller for Wireless Communication
The M44C090-H and M44C890-H are members of Atmels family of 4-bit single-chip microcontrollers. They offer
highest integration for IR and RF data communication and remote-control applications. The M44C090-H /
M44C890-H is suitable for the transmitter side. It contains ROM, RAM, parallel I/O ports, one 8-bit programmable
multifunction timer/counter with modulator function, voltage supervisor, interval timer with watchdog function and
a sophisticated on-chip clock generation with external clock input, integrated RC-, 32-kHz crystal- and 4-MHz crystal-
oscillators. The M44C890-H has an additional EEPROM as a second chip in one package.
Features / Benefits
D Extended temperature range for high temperature up
to 105_C
D 2-Kbyte ROM, 256 x 4-bit RAM
D 12 bidirectional I/Os
D Up to 6 external / internal interrupt sources
D Multifunction timer/counter with
– IR remote control carrier generator
– Biphase-, Manchester- and pulse-width modulator
D Programmable system-clock with prescaler and five
different clock sources
D Wide supply voltage range (1.8 to 6.5 V)
D Very low sleep current (< 1 µA)
D 32 x 16-bit EEPROM (M44C890-H only)
D Synchronous serial interface (2-wire, I2C, 3-wire)
D Watchdog, POR and brown-out function
D Voltage monitoring incl. Lo_BAT detect
D Flash controller T48C893 available (SSO20)
VSS VDD
OSC1 OSC2
BP20/NTE
BP21
BP22
BP23
Brown-out protect.
RESET
Voltage monitor
External input
VMI
RC Crystal External
oscillators oscillators clock input
Clock management
ROM
2 K x 8 bit
RAM
256 x 4 bit
MARC4
4-bit CPU core
I/O bus
UTCM
Timer 1
interval- and
watchdog timer
Timer 2
8/12-bit timer
with modulator
SSI
Serial interface
T2I
T2O
SD
SC
Data direction +
alternate function
Port 4
Data direction +
interrupt control
Port 5
BP40 BP42
INT3 T2O BP43
SC BP41 INT3
VMI SD
T2I
BP50 BP52
INT6 INT1
BP51 BP53
INT6 INT1
Figure 1. Block diagram M44C090-H/M44C890-H
13389
Rev.A3, 14-Dec-01
1 (63)

1 page




M44C090-H pdf
M44C090-H
M44C890-H
1 Introduction
The M44C090-H / M44C890-H are members of Atmels
family of 4-bit single-chip microcontrollers. They con-
tain ROM, RAM, parallel I/O ports, one 8-bit
programmable multifunction timer/counter, voltage su-
pervisor, interval timer with watchdog function and a
sophisticated on-chip clock generation with integrated
RC-, 32-kHz crystal- and 4-MHz crystal-oscillators.
Table 2 provides an overview of the available variants.
Table 2 Available variants of M4xCx9x
Version
Type
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁFlash device
T48C893
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁProduction
M44C090-H
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁProduction
M44C890-H
ROM
4 Kbyte EEPROM
2 Kbyte mask ROM
2 Kbyte mask ROM
E2PROM peripheral Packages
64 byte
SSO20
––– SSO20
64 byte
SSO20
2 MARC4 Architecture
peripherals. This enhances program execution speed by
allowing both instruction prefetching, and a simultaneous
2.1 General Description
communication to the on-chip peripheral circuitry. The
extremely powerful integrated interrupt controller with
The MARC4 microcontroller consists of an advanced associated eight prioritized interrupt levels supports fast
stack-based, 4-bit CPU core and on-chip peripherals. The and efficient processing of hardware events. The MARC4
CPU is based on the HARVARD architecture with is designed for the high-level programming language
physically separate program memory (ROM) and data qFORTH. The core includes both, an expression and a
memory (RAM). Three independent buses, the return stack. This architecture enables high-level
instruction bus, the memory bus and the I/O bus, are used language programming without any loss of efficiency or
for parallel communication between ROM, RAM and code density.
SRcyleossCtcSeeRlkltomeeceskpeÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏt ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏPmÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏreoÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏIcmIgndnosretÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏnoItaecrntrrmurosryoÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏcdutblrtepluuiIeortÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ/scrOntioÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏbMnusÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏAPCÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏRMCeÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏm4oÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏrCCyÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏCbORSXYuRPPÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏsREÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏTOÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏSAÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏL2R5UÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ6AxÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ4M-bÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏit ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
Onchip peripheral modules
Figure 3. MARC4 core
94 8973
Rev.A3, 14-Dec-01
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5 Page





M44C090-H arduino
M44C090-H
M44C890-H
Table 3 Interrupt priority table
Interrupt
INT0
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁINT1
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁINT2
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁINT3
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁINT4
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁINT5
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁINT6
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁINT7
Priority
lowest
|
|
|
|
|
highest
ROM Address Interrupt Opcode
040h
C8h (SCALL 040h)
080h
D0h (SCALL 080h)
0C0h
100h
D8h (SCALL 0C0h)
E8h (SCALL 100h)
140h
180h
1C0h
E8h (SCALL 140h)
F0h (SCALL 180h)
F8h (SCALL 1C0h)
1E0h
FCh (SCALL 1E0h)
Function
Software interrupt (SWI0)
External hardware interrupt, any edge at BP52
or BP53
Timer 1 interrupt
SSI interrupt or external hardware interrupt at
BP40 or BP43
Timer 2 interrupt
Software interrupt (SW15)
External hardware interrupt, at any edge at
BP50 or BP51
Voltage monitor (VM) interrupt
Table 4 Hardware interrupts
Interrupt
Interrupt Mask
Interrupt Source
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁINT1
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁINT2
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁINT3
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁINT4
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁINT6
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁINT7
Register
P5CR
T1M
SISC
T2CM
P5CR
VCM
Bit
P52M1, P52M2
P53M1, P53M2
T1IM
SIM
T2IM
P50M1, P50M2
P51M1, P51M2
VIM
Any edge at BP52
any edge at BP53
Timer 1
SSI buffer full / empty or BP40/BP43 interrupt
Timer 2 compare match / overflow
Any edge at BP50,
any edge at BP51
External / internal voltage monitoring
Software Interrupts
The programmer can generate interrupts by using the
software interrupt instruction (SWI) which is supported
in qFORTH by predefined macros named SWI0...SWI7.
The software triggered interrupt operates exactly like any
hardware triggered interrupt. The SWI instruction takes
the top two elements from the expression stack and writes
the corresponding bits via the I/O bus to the interrupt
pending register. Therefore, by using the SWI instruction,
interrupts can be re-prioritized or lower priority processes
scheduled for later execution.
Hardware Interrupts
In the M44C090-H, there are eleven hardware interrupt
sources with seven different levels. Each source can be
masked individually by mask bits in the corresponding
control registers. An overview of the possible hardware
configurations is shown in table 4.
2.3 Master Reset
The master reset forces the CPU into a well-defined
condition. It is unmaskable and is activated independent
of the current program state. It can be triggered by either
initial supply power-up, a short collapse of the power sup-
ply, brown-out detection circuitry, watchdog time-out, or
an external input clock supervisor stage (see figure 9). A
master reset activation will reset the interrupt enable flag,
the interrupt pending register and the interrupt active
register. During the power-on reset phase the I/O bus con-
trol signals are set to reset modethereby initializing all
on-chip peripherals. All bidirectional ports are set to input
mode. Attention: During any reset phase, the BP20/NTE
input is driven towards VDD by a strong pull-up transistor.
Releasing the reset results in a short call instruction
(opcode C1h) to the ROM address 008h. This activates
the initialization routine $RESET which in turn has to
initialize all necessary RAM variables, stack pointers and
peripheral configuration registers (see table 7).
Rev.A3, 14-Dec-01
11 (63)

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