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PDF S1D13505 Data sheet ( Hoja de datos )
| Número de pieza | S1D13505 | |
| Descripción | LCD Controller | |
| Fabricantes | Epson Electronics | |
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S1D13505 Embedded RAMDAC LCD/CRT Controller
S1D13505
TECHNICAL MANUAL
Document Number: X23A-Q-001-12
Copyright © 1998, 2001 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice. You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
1 page  
ENERGY
SAVI NG
EPSON
GRAPHICS
S1D13505
S1D13505 EMBEDDED RAMDAC LCD/CRT CONTROLLER October 2001
s DESCRIPTION
The S1D13505 is a color/monochrome LCD/CRT graphics controller interfacing to a wide range of CPUs and display
devices. The S1D13505 architecture is designed to meet the low cost, low power requirements of the embedded
markets, such as Mobile Communications, Hand-Held PCs, and Office Automation.
The S1D13505 supports multiple CPUs, all LCD panel types, CRT, and additionally provides a number of
differentiating features. Products requiring a “Portrait” mode display can take advantage of the SwivelView feature.
Simultaneous, Virtual and Split Screen Display are just some of the display modes supported, while the Hardware
Cursor, Ink Layer, and the Memory Enhancement Registers offer substantial performance benefits. These features,
combined with the S1D13505’s Operating System independence, make it an ideal display solution for a wide variety
of applications.
s FEATURES
Display Modes
Memory Interface
• 16-bit EDO-DRAM or FPM-DRAM interface.
• Memory size options:
512K bytes using one 256K×16 device.
2M bytes using one 1M×16 device.
• Addressable as a single linear address space.
CPU Interface
• Supports the following interfaces:
Hitachi SH-4.
Hitachi SH-3.
Motorola M68K.
Philips MIPS PR31500/PR31700.
• 1/2/4/8/16 bit-per-pixel (bpp) support on LCD/CRT.
• Up to 16 shades of gray using FRM on monochrome
passive LCD panels.
• Up to 4096 colors on passive LCD panels.
• Up to 64K colors on active matrix TFT/D-TFD LCD
panels and CRT in 16 bpp modes.
• Split Screen Display: allows two different images to be
simultaneously viewed on the same display.
• Virtual Display Support: displays images larger than the
display size through the use of panning.
• Double Buffering/multi-pages: provides smooth
animation and instantaneous screen update.
Toshiba MIPS TX3912.
Motorola Power PC MPC821.
NEC MIPS VR4102/VR4111.
Epson E0C33.
PC Card (PCMCIA).
StrongARM (PC Card).
ISA bus.
MPU bus interface with programmable READY.
• CPU write buffer.
Display Support
• 4/8-bit monochrome passive LCD interface.
• 4/8/16-bit color passive LCD interface.
• Single-panel, single-drive displays.
• Dual-panel, dual-drive displays.
• Direct support for 9/12-bit TFT/D-TFD; 18-bit TFT/D-TFD
is supported up to 64K color depth (16-bit data).
• Embedded RAMDAC with direct analog CRT drive.
• Simultaneous display of CRT and passive or TFT/D-TFD
panels.
• Maximum resolution of 800x600 pixels at a color
• SwivelView: direct hardware 90° rotation of
display image for portrait mode display.
• Acceleration of screen updates by allocating full
display memory bandwidth to CPU.
• Hardware 64x64 pixel 2-bit cursor or full screen
2-bit ink layer.
Clock Source
• Single clock input for both pixel and memory clocks.
• Memory clock can be input clock or (input clock/2),
providing flexibility to use CPU bus clock as input.
• Pixel clock can be memory clock or (memory clock/2) or
(memory clock/3) or (memory clock/4).
Power Down Modes
• Software power save mode.
• LCD power sequencing.
General Purpose IO Pins
• Up to 3 General Purpose IO pins are available.
Operating Voltage
• 2.7 volts to 5.5 volts.
depth of 16 bpp.
Package
• 128-pin QFP15 surface mount package.
X23A-C-002-15
1
5 Page 
Epson Research and Development
Vancouver Design Center
Page 5
8.2.5 Clock Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
8.2.6 Power Save Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
8.2.7
8.2.8
8.2.9
Miscellaneous Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Look-Up Table Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Ink/Cursor Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
9 Display Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
9.1 Image Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
9.2 Ink/Cursor Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
9.3 Half Frame Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
10 Display Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
10.1 Display Mode Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
10.2 Image Manipulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
11 Look-Up Table Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
11.1 Monochrome Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
11.2 Color Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
12 Ink/Cursor Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
12.1 Ink/Cursor Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
12.2 Ink/Cursor Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
12.3 Ink/Cursor Image Manipulation . . . . . . . . . . . . . . . . . . . . . . . . . . .134
12.3.1 Ink Image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
12.3.2 Cursor Image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
13 SwivelView™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
13.1 Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
13.2 Image Manipulation in SwivelView . . . . . . . . . . . . . . . . . . . . . . . . . .136
13.3 Physical Memory Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . .137
13.4 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
14 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
14.1 Maximum MCLK: PCLK Ratios . . . . . . . . . . . . . . . . . . . . . . . . . . .139
14.2 Frame Rate Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
14.3 Bandwidth Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
15 Power Save Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
16 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
Hardware Functional Specification
Issue Date: 01/02/02
S1D13505
X23A-A-001-14
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet S1D13505.PDF ] | |
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| S1D13505 | LCD Controller | Epson Electronics |
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