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PDF T15M256B Data sheet ( Hoja de datos )
| Número de pieza | T15M256B | |
| Descripción | 32K X 8 LOW POWER CMOS STATIC RAM | |
| Fabricantes | TM tech | |
| Logotipo |  |
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tm TE
CH
T15M256B
SRAM
32K X 8 LOW POWER
CMOS STATIC RAM
FEATURES
• High speed access time: 50/70/85/100ns
• Low power supply current :
- Operating :35mA(max)
- Standby : 10uA
• Power supply : 5V (± 10%)
• Fully static operation – No clock or refreshing
required
• All inputs and outputs directly LVTTL
compatible
• Common I/O capability
• Data retention voltage : 1.5V (min)
• Available packages :
28-pin DIP(600mil),SOJ, SOP, TSOP-I
(8x13.4mm forward type and reverse type).
• Operating temperature :
- 0 ~ +70 °C
- -40 ~ +85 °C
PART NUMBER EXAMPLES
PART NO.
T15M256B-70N
T15M256B-70J
T15M256B-70D
T15M256B-85P
T15M256B-85R
T15M256B-70NI
T15M256B-70JI
T15M256B-70DI
T15M256B-85PI
T15M256B-85RI
PACKAGE
CODE
N=DIP
J=SOJ
D=SOP
P= TSOP-I(Forward)
R= TSOP-I(Reverse)
N=DIP
J=SOJ
D=SOP
P= TSOP-I(Forward)
R= TSOP-I(Reverse)
Operating
Temperature
0 ~ +70 °C
-40 ~ +85 °C
GENERAL DESCRIPTION
The T15M256B is a low power CMOS static
RAM. organized as 32,768 x 8 bits that operates
on a single 5-volt power supply. Low operating
and standby current . Data retention is guaranteed
at a power supply voltage as low as 1.5V. This
device is packaged in a standard 28-pin
DIP(600mil), SOJ, SOP, TSOP-I forward and
reverse type.
BLOCK DIAGRAM
Vcc →
Vss →
A0 →
.
. DECODER
.
A14 →
CS →
OE → CONTROL
WE →
CORE
ARRAY
← I / O1
.
DATA I/O
.
← I / O8
TM Technology Inc. reserves the right
P. 1
to change products or specifications without notice.
Publication Date: MAY. 2002
Revision:A
1 page  
tm TE
CH
T15M256B
AC CHARACTERISTICS
(Vcc= 5V / ± 10%, Vss = 0V, Ta =0 ~ +70 °C/ -40 to 85°C)
(1) READ CYCLE
PARAMETER
Read Cycle Time
SYM.
tRC
-50ns
MIN MAX
50 -
-70ns
MIN. MAX.
70 -
-85ns
-100ns UNIT
MIN. MAX. MIN. MAX.
85 - 100 - ns
Address Access Time
tAA - 50 - 70 - 85 - 100 ns
Chip Select Access Time
tACS - 50 - 70 - 85 - 100 ns
Output Enable to Output Valid
tAOE - 25 - 35 - 40 - 50 ns
Chip Selection to Output in Low Z tCLZ* 7 - 10 - 10 - 10 - ns
Output Enable to Output in Low Z tOLZ* 5 - 5 - 5 - 5 - ns
Chip Deselection to Output in High Z tCHZ* - 20 - 25 - 30 - 30 ns
Output Disable to Output in High Z tOHZ* - 20 - 25 - 30 - 30 ns
Output Hold from Address Change tOH 10 - 10 - 10 - 10 - ns
* These parameters is measured with 5pF test load.
(2)WRITE CYCLE
PARAMETER
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
Data Valid to End of Write
Data Hold from End of Write
Write to Output in High Z
Output Active from End of Write
SYM.
tWC
-50ns
MIN MAX
50 -
-70ns
-85ns
-100ns UNIT
MIN. MAX. MIN. MAX. MIN. MAX.
70 - 85 - 100 - ns
tCW 40 - 60 - 70 - 80 - ns
tAW 40 - 60 - 70 - 80 - ns
tAS 0 - 0 - 0 - 0 - ns
tWP 30 - 50 - 60 - 70 - ns
tWR 0 - 0 - 0 - 0 - ns
tDW 25 - 30 - 35 - 40 - ns
tDH 0 - 0 - 0 - 0 - ns
tWHZ* - 20 - 25 - 30 - 30 ns
tOW 5 - 5 - 5 - 5 - ns
* These parameters is measured with 30pF test load.
TM Technology Inc. reserves the right
P. 5
to change products or specifications without notice.
Publication Date: MAY. 2002
Revision:A
5 Page 
tm TE
CH
PACKAGE DIMENSIONS
28-LEAD SOJ SRAM (300 mil)
T15M256B
SYMBOL
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
y
DIMENSIONS IN INCHES
0.710±0.002
0.300±0.005
0.060±0.002
0.050±0.001
0.063±0.001
0.015±0.002
0.030±0.002
0.050±0.002
0.018±0.002
0.028±0.002
0.337±0.002
0.010±0.001
0.026±0.002
0.268±0.003
0.300±0.002
0.053±0.001
0.140±0.004
0.004(MAX)
DIMENSIONS IN MM
18.03±0.05
7.62±0.13
1.52±0.05
1.27±0.03
1.63±0.03
0.38±0.05
0.76±0.05
1.27±0.05
0.46±0.05
0.71±0.05
8.56±0.05
0.25±0.03
0.66±0.05
6.81±0.08
7.62±0.05
1.35±0.03
3.56±0.10
0.10(MAX)
TM Technology Inc. reserves the right
P. 11
to change products or specifications without notice.
Publication Date: MAY. 2002
Revision:A
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet T15M256B.PDF ] | |
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