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PDF S3067TB20 Data sheet ( Hoja de datos )
| Número de pieza | S3067TB20 | |
| Descripción | Multirate Sonet / SDH / ATM Transceiver w/FEC | |
| Fabricantes | Applied Micro Circuits | |
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DEVICE
SMPUELCTIFIIRCAATTIEON(OC-48/24/12/3/GBE/FC) SONET/SDH/ATM TRANSCEIVER w/ FEC
SMBOUiCNLMETIOTR/SASDTLEHVP/(AOETCCM-L48OC/C2L4-O1/1C22K/3T/GRGEABNEES/FRMCAI)TTSTOOERNREATN/SDDRHE/ACTEMIVTERRANSCEIVER w/ FEC
®
S3067
SS33006677
FEATURES
• SiGe BiCMOS technology
• Complies with Bellcore and ITU-T
specifications
• On-chip high-frequency PLL for clock generation
• Supports:
- OC-48 (with FEC)
- OC-24 (with FEC)
- OC-12 (with FEC)
- OC-3 (with FEC)
- Fibre Channel
• FEC capability up to 8 bytes per 255-byte block
• Reference frequency – 131.25 MHz to 178 MHz
• Interface to LVPECL and TTL logic
• 16-Bit single-ended LVPECL data path
• Compact 156 Pin TBGA package
• Diagnostic loopback mode
• Supports line timing
• Lock Detect
• Signal detect input
• Low jitter LVPECL interface
• Internal FIFO to decouple transmit clocks
• Single 3.3 V supply
• Typical power 1.5 W
APPLICATIONS
• Wavelength Division Multiplexing equipment
• SONET/SDH-based transmission systems
• SONET/SDH modules
• SONET/SDH test equipment
• ATM over SONET/SDH
• Section repeaters
• Add Drop Multiplexers (ADM)
• Broad-band cross-connects
• Fiber optic terminators
• Fiber optic test equipment
GENERAL DESCRIPTION
The S3067 SONET/SDH transceiver chip is a fully
integrated multirate serialization/deserialization SO-
NET OC-48, OC-24, OC-12 and OC-3 interface
device. The chip performs all necessary serial-to-
parallel and parallel-to-serial functions in
conformance with SONET/SDH transmission and
Forward Error Correction (FEC) standards. The de-
vice is suitable for SONET-based WDM applications.
Figure 1 shows a typical network application.
On-chip clock synthesis is performed by the high-
frequency phase-locked loop on the S3067
transceiver chip allowing the use of a slower external
transmit clock reference. The chip can be used with a
131.25 MHz to 178 MHz reference clock in support
of existing system clocking schemes.
The low jitter LVPECL interface guarantees compli-
ance with the bit-error rate requirements of the
Bellcore and ITU-T standards. The S3067 is pack-
aged in a 156 Pin TBGA, offering designers a small
package outline.
The S3067 supports FEC designs with internal divid-
ers or external clocking modes.
Figure 1. System Block Diagram
2.488 Gbps
X
S3076
Clock
Recovery
Unit
2.488
Gbps
X
PERFORMANCE MONITOR
S3067
155 Mbps
Receive
Deserialization
X
S3062
Receive
S3062 167 Mbps S3067 2.67 Gbps
Transmit
FEC Added
X+Y
Transmit
Serialization X + Y
E/O
OPTICAL FIBER
PERFORMANCE MONITOR
O/E
S3076
S3067
S3062
Clock 2.67 Gbps Receive
167 Mbps Receive
Recovery X + Y Deserialization X + Y FEC Data
Unit Stripped Off
S3062
Transmit
155 Mbps
S3067
Transmit
2.488 Gbps
X Serialization X
X = Data
Y = FEC Data
September 17, 2002/ Revision A
1
1 page  
MULTIRATE (OC-48/24/12/3/GBE/FC) SONET/SDH/ATM TRANSCEIVER w/ FEC
Figure 5. Clock Synthesizer
S3067
REFCLK
VCO
PD LPF
VCOCLK
RSCLK
N
RSCLK Divider
FECSEL 2
FECSEL (0-1)
M
VCO Divider
Where N = 14/15/16/17 RSCLK = N
M = 14/15/16/17 VCOCLK M
A high on FECSEL2 selects RSCLK divided by N. A
low on FECSEL2 selects the REFCLK. The REFCLK
or RSCLK divided by N is divided by 1/M (multiplied
by M) in the loop. The value of M and N can be
selected by FECSEL0 and FECSEL1.
When FECSEL2 = 0, VCOCLK = REFCLK * M. The
user must select the proper value of REFCLK and M
to get the desired VCOCLK frequency. When
FECSEL2 = 1, VCOCLK = (RSCLK * M) ÷ N. The
user must select the proper M/N ratio (with
FECSEL0 and FECSEL1) to get the desired
VCOCLK value. (See Tables 3 and 4.)
Example: OC-48 FEC capability of 8 bytes per
255-byte block. Required VCOCLK = 2.6656 GHz.
Method 1:
Required VCOCLK = 2.6656 GHz
FECSEL2 = 0, selects REFCLK
FECSEL0 = 1 and FECSEL1 = 0, selects VCO
divider(M) = 16
REFCLK = 2.6656 GHz ÷ 16 = 166.60 MHz
VCOCLK = REFCLK ÷ (1/M) = 166.60 * 16 = 2.6656
GHz
Method 2:
Required VCOCLK = 2.6656 GHz
FECSEL2 = 1, selects RSCLK
FECSEL0 = 0 and FECSEL1 = 0, selects VCO
divider(M) = 17 and RSCLK divider(N) = 16
RSCLK = (2.6656 * 16) ÷ 17 = 2.5088 GHz
VCOCLK = RSCLK ÷ N ÷ (1/M) = 2.5088 GHz ÷ 16 *
17 = 2.6656 GHz.
September 17, 2002/ Revision A
5
5 Page 
MULTIRATE (OC-48/24/12/3/GBE/FC) SONET/SDH/ATM TRANSCEIVER w/ FEC
Table 8. S3067 Common Pin Assignment and Descriptions
S3067
Pin Name
Level I/O Pin #
Description
SQUELCH
LVTTL I
REFCLKP
REFCLKN
DLEB
Internally
Biased
Diff.
LVPECL
LVTTL
I
I
LLEB
LVTTL I
KILLRXCLK
LVTTL I
SLPTIME
LVTTL I
RLPTIME
LVTTL I
RSTB
TESTEN
155MCKP
155MCKN
LVTTL I
LVTTL I
Diff. O
LVPECL
19MCK
LOCKDET
Single
Ended
LVPECL
O
LVTTL O
R16 RSCLK Clock Squelch. Active High. When SQUELCH is active
and SD is inactive, the transmit clock will be used in place of the
RSCLK.
M2 Reference Clock Input. Used as the reference for the internal bit
L3 clock frequency synthesizer.
N15 Diagnostic Loopback Enable. Active Low. Selects diagnostic
loopback. When DLEB is High, the S3067 device uses the primary
data (RSD) and clock (RSCLK) inputs. When Low, the S3067
device uses the diagnostic loopback clock and data from the
transmitter. TSD/TSCLK are active in DLEB.
N14 Line Loopback Enable. Active Low. Selects line loopback. When
LLEB is Low, the S3067 will route the data from the RSD/RSCLK
inputs to the TSD/TSCLK outputs.
M14 Kill Receive Clock Input. For normal operation, KILLRXCLK is
High. When this input is Low, it will force POCLK output to a logic
"0" state.
T1 Serial Clock Loop Time Select input. Active High. When High,
SLPTIME enables the recovered clock from the receive section to
be used in place of the synthesized transmit clock.
T2 Reference Clock Looptime Select input. Active High. When High,
RLPTIME enables POCLK from the receiver to be used as the
reference clock input to the transmitter.
P15 Master Reset. Reset input for the device, Active Low. During
Reset, all clocks are disabled.
N2 Test Enable. Used for production testing. Low for normal
operation.
R14 VCO ÷ by 16 Clock Output from the clock synthesizer. This output
T15 should be connected to the reference clock input of the external
clock recovery function (such as the S3066). It is recommended
to tie 155MCKP/N to VCC when not used.
P14 VCO ÷ by 128 Clock Output from the clock synthesizer. This
output should be connected to the reference clock input of the
external clock recovery function. It is recommended to tie 19MCK
to VCC when not used.
H1 Lock Detect. Active High. Goes active after the PLL has locked to
the clock provided on the REFCLK pins. LOCKDET is an
asynchronous output.
September 17, 2002/ Revision A
11
11 Page | ||
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| PDF Descargar | [ Datasheet S3067TB20.PDF ] | |
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